Transmission device, transmission method, reception device, and reception method

ABSTRACT

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 9/16 or 10/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns. The present technology can be applied to data transmission using an LDPC code.

TECHNICAL FIELD

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method, and more particularly to, for example, a transmission device, a transmission method, a reception device, and a reception method for securing favorable communication quality in data transmission using an LDPC code.

BACKGROUND ART

Low density parity check (LDPC) codes have high error correction capability and are in recent years widely adopted in transmission systems for digital broadcasting and the like, such as the digital video broadcasting (DVB)-S.2 in Europe and the like, DVB-T.2, DVB-C.2, and the advanced television systems committee (ATSC) 3.0 in the United States, and the like, for example (see, for example, Non-Patent Document 1).

With recent researches, it has been found that the LDPC codes are able to obtain performance close to the Shannon limit as the code length is increased, similarly to turbo codes and the like. Furthermore, the LDPC codes have a property that the minimum distance is proportional to the code length and thus have a good block error probability characteristic, as characteristics. Moreover, a so-called error floor phenomenon observed in decoding characteristics of turbo codes and the like hardly occur, which is also an advantage.

CITATION LIST Non-Patent Document

-   Non-Patent Document 1: ATSC Standard: Physical Layer Protocol     (A/322), 7 Sep. 2016

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

In data transmission using an LDPC code, for example, the LDPC code is symbols (symbolized) of quadrature modulation (digital modulation) such as quadrature phase shift keying (QPSK), and the symbols are mapped at signal points of the quadrature modulation and are sent.

The data transmission using an LDPC code is spreading worldwide and is required to secure favorable communication (transmission) quality.

The present technology has been made in view of such a situation, and aims to secure favorable communication quality in data transmission using an LDPC code.

Solutions to Problems

A first transmission device/transmission method of the present technology is a transmission device/transmission method including: an encoding unit/step of performing LDPC coding on the basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 9/16, in which the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

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In the first transmission device and transmission method of the present technology, LDPC coding is performed on the basis of a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 9/16. The LDPC code includes the information bits and parity bits, the parity check matrix includes the information matrix portion corresponding to the information bits and the parity matrix portion corresponding to the parity bits, the information matrix portion is represented by the parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

291 817 1023 1118 1168 1195 1419 1763 2507 3005 3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301 6600 6644 7052 7093 7105 7487 133 565 957 1018 1150 1196 1210 1224 1361 1484 2330 2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399 5421 5545 6972 7156 129 365 541 1026 1199 1527 2467 3386 3458 4215 4438 4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745 6973 7251 7329 7336 996 1392 2493 2910 3048 3281 4969 5189 5632 6236 6983 165 2521 2650 2824 3493 4637 5670 6470 266 345 390 2365 2843 3274 4321 5165 245 2173 2274 2687 3763 4284 5562 6564 2787 2970 3503 691 3718 5047 593 969 3593 331 3809 6269 1627 2886 5935 1046 2976 4457 4725 6028 6458 6172 6610 7530 1536 7102 7148 233 2463 4955 826 4319 6969 3073 6675 6774 407 4251 7087 1380 3802 4937 1911 4360 6306 4027 6219 7292 398 1190 1936 250 830 7241 5500 5828 7478 1261 4649 7237.

A first reception device/reception method of the present technology is a reception device/reception method including: a decoding unit/step of decoding an LDPC code with a code length N of 17280 bits and a coding rate r of 9/16, the LDPC code being obtained from data transmitted by a transmission method including an encoding step of performing LDPC coding on the basis of a parity check matrix of the LDPC code, in which the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

291 817 1023 1118 1168 1195 1419 1763 2507 3005 3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301 6600 6644 7052 7093 7105 7487 133 565 957 1018 1150 1196 1210 1224 1361 1484 2330 2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399 5421 5545 6972 7156 129 365 541 1026 1199 1527 2467 3386 3458 4215 4438 4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745 6973 7251 7329 7336 996 1392 2493 2910 3048 3281 4969 5189 5632 6236 6983 165 2521 2650 2824 3493 4637 5670 6470 266 345 390 2365 2843 3274 4321 5165 245 2173 2274 2687 3763 4284 5562 6564 2787 2970 3503 691 3718 5047 593 969 3593 331 3809 6269 1627 2886 5935 1046 2976 4457 4725 6028 6458 6172 6610 7530 1536 7102 7148 233 2463 4955 826 4319 6969 3073 6675 6774 407 4251 7087 1380 3802 4937 1911 4360 6306 4027 6219 7292 398 1190 1936 250 830 7241 5500 5828 7478 1261 4649 7237.

In the first reception device and the first reception method of the present technology, the LDPC code obtained from the data transmitted by the first transmission method is decoded.

A second transmission device/transmission method of the present technology is a transmission device/transmission method including: an encoding unit/step of performing LDPC coding on the basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 10/16, in which the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

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In the second transmission device and the second transmission method of the present technology, the LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 10/16. The LDPC code includes the information bits and parity bits, the parity check matrix includes the information matrix portion corresponding to the information bits and the parity matrix portion corresponding to the parity bits, the information matrix portion is represented by the parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

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A second reception device/reception method of the present technology is a reception device/reception method including: a decoding unit/step of decoding an LDPC code with a code length N of 17280 bits and a coding rate r of 10/16, the LDPC code being obtained from data transmitted by a transmission method including an encoding step of performing LDPC coding on the basis of a parity check matrix of the LDPC code, in which the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is

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In the second reception device and the second reception method of the present technology, the LDPC code obtained from the data transmitted by the second transmission method is decoded.

Note that the transmission device and the reception device may be independent devices or may be internal blocks configuring one device.

Effects of the Invention

According to the present technology, good communication quality can be secured in data transmission using an LDPC code.

Note that effects described here are not necessarily limited, and any of effects described in the present disclosure may be exhibited.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram for describing a parity check matrix H of an LDPC code.

FIG. 2 is a flowchart for describing a procedure of decoding an LDPC code.

FIG. 3 is a diagram illustrating an example of a parity check matrix of an LDPC code.

FIG. 4 is a diagram illustrating an example of a Tanner graph of the parity check matrix.

FIG. 5 is a diagram illustrating an example of a variable node.

FIG. 6 is a diagram illustrating an example of a check node.

FIG. 7 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied.

FIG. 8 is a block diagram illustrating a configuration example of a transmission device 11.

FIG. 9 is a block diagram illustrating a configuration example of a bit interleaver 116.

FIG. 10 is a diagram illustrating an example of a parity check matrix.

FIG. 11 is a diagram illustrating an example of a parity matrix.

FIG. 12 is a diagram for describing a parity check matrix of an LDPC code defined in the standard of DVB-T.2.

FIG. 13 is a diagram for describing a parity check matrix of an LDPC code defined in the standard of DVB-T.2.

FIG. 14 is a diagram illustrating an example of a Tanner graph regarding decoding of an LDPC code.

FIG. 15 is a diagram illustrating examples of a parity matrix H_(T) having a step structure and a Tanner graph corresponding to the parity matrix H_(T).

FIG. 16 is a diagram illustrating the parity matrix H_(T) of the parity check matrix H corresponding to the LDPC code after parity interleaving.

FIG. 17 is a flowchart for describing an example of processing performed by a bit interleaver 116 and a mapper 117.

FIG. 18 is a block diagram illustrating a configuration example of an LDPC encoder 115.

FIG. 19 is a flowchart for describing an example of processing of the LDPC encoder 115.

FIG. 20 is a diagram illustrating an example of a parity check matrix initial value table with a coding rate of 1/4 and a code length of 16200.

FIG. 21 is a diagram for describing a method of obtaining the parity check matrix H from the parity check matrix initial value table.

FIG. 22 is a diagram illustrating a structure of a parity check matrix.

FIG. 23 is a diagram illustrating an example of a parity check matrix initial value table.

FIG. 24 is a diagram illustrating an A matrix generated from the parity check matrix initial value table.

FIG. 25 is a diagram for describing parity interleaving of a B matrix.

FIG. 26 is a diagram for describing a C matrix generated from the parity check matrix initial value table.

FIG. 27 is a diagram for describing parity interleaving of a D matrix.

FIG. 28 is a diagram illustrating a parity check matrix in which column permutation as parity deinterleaving for restoring parity interleaving is performed.

FIG. 29 is a diagram illustrating a transformed parity check matrix obtained by performing row permutation for the parity check matrix.

FIG. 30 is a diagram illustrating an example of a parity check matrix initial value table of a type A code with N=17280 bits and r=2/16.

FIG. 31 is a diagram illustrating an example of a parity check matrix initial value table of a type A code with N=17280 bits and r=3/16.

FIG. 32 is a diagram illustrating an example of a parity check matrix initial value table of a type A code with N=17280 bits and r=4/16.

FIG. 33 is a diagram illustrating an example of a parity check matrix initial value table of a type A code with N=17280 bits and r=5/16.

FIG. 34 is a diagram illustrating an example of a parity check matrix initial value table of a type A code with N=17280 bits and r=6/16.

FIG. 35 is a diagram illustrating an example of a parity check matrix initial value table of a type A code with N=17280 bits and r=7/16.

FIG. 36 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=7/16.

FIG. 37 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=8/16.

FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=9/16.

FIG. 39 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=10/16.

FIG. 40 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=11/16.

FIG. 41 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=12/16.

FIG. 42 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=13/16.

FIG. 43 is a diagram illustrating an example of a parity check matrix initial value table of a type B code with N=17280 bits and r=14/16.

FIG. 44 is a diagram illustrating an example of a Tanner graph of an ensemble of degree sequence with a column weight of 3 and a row weight of 6.

FIG. 45 is a diagram illustrating an example of a Tanner graph of a multi-edge type ensemble.

FIG. 46 is a diagram for describing a parity check matrix by a type A method.

FIG. 47 is a diagram for describing parity check matrices by the type A method.

FIG. 48 is a diagram for describing a parity check matrix by a type B method.

FIG. 49 is a diagram for describing parity check matrices by the type B method.

FIG. 50 is a diagram illustrating examples of a coordinate of a signal point of UC in a case where a modulation method is QPSK.

FIG. 51 is a diagram illustrating examples of a coordinate of a signal point of 2D-NUC in a case where the modulation method is 16QAM.

FIG. 52 is a diagram illustrating examples of a coordinate of a signal point of 1D-NUC in a case where the modulation method is 1024QAM.

FIG. 53 is a diagram illustrating a relationship between a symbol y of 1024QAM and a position vector u.

FIG. 54 is a diagram illustrating examples of a coordinate z_(q) of a signal point of QPSK-UC.

FIG. 55 is a diagram illustrating examples of a coordinate z_(q) of a signal point of QPSK-UC.

FIG. 56 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 16QAM-UC.

FIG. 57 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 16QAM-UC.

FIG. 58 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 64QAM-UC.

FIG. 59 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 64QAM-UC.

FIG. 60 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 256QAM-UC.

FIG. 61 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 256QAM-UC.

FIG. 62 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 1024QAM-UC.

FIG. 63 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 1024QAM-UC.

FIG. 64 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 4096QAM-UC.

FIG. 65 is a diagram illustrating examples of a coordinate z_(q) of a signal point of 4096QAM-UC.

FIG. 66 is a diagram illustrating examples of a coordinate z_(s) of a signal point of 16QAM-2D-NUC.

FIG. 67 is a diagram illustrating examples of a coordinate z_(s) of a signal point of 64QAM-2D-NUC.

FIG. 68 is a diagram illustrating examples of a coordinate z_(s) of a signal point of 256QAM-2D-NUC.

FIG. 69 is a diagram illustrating examples of a coordinate z_(s) of a signal point of 256QAM-2D-NUC.

FIG. 70 is a diagram illustrating examples of a coordinate z_(s) of a signal point of 1024QAM-1D-NUC.

FIG. 71 is a diagram illustrating a relationship between a symbol y of 1024QAM and a position vector u.

FIG. 72 is a diagram illustrating examples of a coordinate z_(s) of a signal point of 4096QAM-1D-NUC.

FIG. 73 is a diagram illustrating a relationship between a symbol y of 4096QAM and a position vector u.

FIG. 74 is a diagram illustrating a relationship between a symbol y of 4096QAM and a position vector u.

FIG. 75 is a diagram for describing block interleaving performed by a block interleaver 25.

FIG. 76 is a diagram for describing block interleaving performed by a block interleaver 25.

FIG. 77 is a diagram for describing group-wise interleaving performed by a group-wise interleaver 24.

FIG. 78 is a diagram illustrating an example of a GW pattern for an LDPC code with a code length N of 69120 bits.

FIG. 79 is a block diagram illustrating a configuration example of a reception device 12.

FIG. 80 is a block diagram illustrating a configuration example of a bit deinterleaver 165.

FIG. 81 is a flowchart for describing an example of processing performed by a demapper 164, a bit deinterleaver 165, and an LDPC decoder 166.

FIG. 82 is a diagram illustrating an example of a parity check matrix of an LDPC code.

FIG. 83 is a diagram illustrating an example of a matrix (transformed parity check matrix) obtained by applying row permutation and column permutation to a parity check matrix.

FIG. 84 is a diagram illustrating an example of a transformed parity check matrix divided into 5×5 units.

FIG. 85 is a block diagram illustrating a configuration example of a decoding device that collectively performs P node operations.

FIG. 86 is a block diagram illustrating a configuration example of the LDPC decoder 166.

FIG. 87 is a diagram for describing block deinterleaving performed by a block deinterleaver 54.

FIG. 88 is a block diagram illustrating another configuration example of the bit deinterleaver 165.

FIG. 89 is a block diagram illustrating a first configuration example of the reception system to which the reception device 12 is applicable.

FIG. 90 is a block diagram illustrating a second configuration example of the reception system to which the reception device 12 is applicable.

FIG. 91 is a block diagram illustrating a third configuration example of the reception system to which the reception device 12 is applicable.

FIG. 92 is a block diagram illustrating a configuration example of an embodiment of a computer to which the present technology is applied.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present technology will be described. Before the description of the embodiment, an LDPC code will be described.

<LDPC Code>

Note that the LDPC code is a linear code and is not necessarily binary. However, description will be given on the assumption that the LDPC code is binary.

An LDPC code is most characterized in that a parity check matrix defining the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of “1”s of matrix elements is very small (a matrix in which most elements are 0).

FIG. 1 is a diagram illustrating a parity check matrix H of the LDPC code.

In the parity check matrix H in FIG. 1, a weight of each column (column weight) (the number of “1”s) (weight) is “3”, and a weight of each row (row weight) is “6”.

In coding with an LDPC code (LDPC coding), a codeword (LDPC code) is generated by generating a generator matrix G on the basis of the parity check matrix H and multiplying binary information bits by the generator matrix G, for example.

Specifically, a coding device for performing the LDPC coding first calculates the generator matrix G that holds an expression GH^(T)=0 with a transposed matrix H_(T) of the parity check matrix H. Here, in a case where the generator matrix G is a K×N matrix, the coding device multiplies the generator matrix G by a bit string (vector u) of information bits including K bits and generates a codeword c (=uG) including N bits. The codeword (LDPC code) generated by the coding device is received at a reception side via a predetermined communication path.

Decoding of the LDPC code can be performed by an algorithm called probabilistic decoding proposed by Gallager, which is a message passing algorithm according to belief propagation on a so-called Tanner graph including a variable node (also called message node) and a check node. Here, as appropriate, the variable node and the check node are hereinafter also simply referred to as nodes.

FIG. 2 is a flowchart illustrating a procedure of decoding an LDPC code.

Note that, hereinafter, a real value (received LLR) expressing “0” likeliness of a value of an i-th code bit of the LDPC code (1 codeword) received on the reception side, using a log likelihood ratio, is also referred to as a received value u_(0i) as appropriate. Furthermore, a message output from the check node is u_(j) and a message output from the variable node is v_(i).

First, in decoding the LDPC code, as illustrated in FIG. 2, in step S11, the LDPC code is received, a message (check node message) u_(j) is initialized to “0”, a variable k that is an integer as a counter for repeated processing is initialized to “0”, and the processing proceeds to step S12. In step S12, a message (variable node message) v_(i) is obtained by performing an operation (variable node operation) illustrated in the expression (1) on the basis of the received value u_(0i) obtained by receiving the LDPC code, and moreover, the message u_(j) is obtained by performing an operation (check node operation) illustrated in the expression (2) on the basis of the message v_(i).

$\begin{matrix} \left\lbrack {{Math}.\ 1} \right\rbrack & \; \\ {v_{i} = {u_{0\; i} + {\sum\limits_{j = 1}^{d_{v} - 1}u_{j}}}} & (1) \\ \left\lbrack {{Math}.\mspace{14mu} 2} \right\rbrack & \; \\ {{\tanh\left( \frac{u_{j}}{2} \right)} = {\prod\limits_{i = 1}^{d_{c} - 1}{\tanh\left( \frac{v_{i}}{2} \right)}}} & (2) \end{matrix}$

Here, d_(v) and d_(c) in the expressions (1) and (2) are arbitrarily selectable parameters respectively indicating the numbers of “1”s in a vertical direction (column) and a cross direction (row) of the parity check matrix H. For example, in the case of the LDPC code ((3, 6) LDPC code) for the parity check matrix H with the column weight of 3 and the row weight of 6 as illustrated in FIG. 1, d_(v)=3 and d_(c)=6.

Note that, in each of the variable node operation in the expression (1) and the check node operation in the expression (2), a message input from an edge (a line connecting the variable node and the check node) that is about to output a message is not an object for the operation. Therefore, an operation range is 1 to d_(v)−1 or 1 to d_(c)−1. Furthermore, the check node operation in the expression (2) is performed by, in practice, creating a table of a function R (v₁, v₂) illustrated in the expression (3) defined by one output for two inputs v₁ and v₂, in advance, and continuously (recursively) using the table as illustrated in the expression (4). [Math. 3] x=2 tan h ⁻¹{tan h(v ₁/2)tan h(v ₂/2}=R(v ₁ ,v ₂)  (3) [Math. 4] u _(j) =R(v ₁ ,R(v ₂ ,R(v ₃ , . . . R(v _(d) _(c) ⁻² ,v _(d) _(c) ⁻¹))))  (4)

In step S12, the variable k is further incremented by “1”, and the processing proceeds to step S13. In step S13, whether or not the variable k is larger than a predetermined number of repetitive decoding times C is determined. In a case where the variable k is determined not to be larger than C in step S13, the processing returns to step S12 and hereinafter similar processing is repeated.

Furthermore, in a case where the variable k is determined to be larger than C in step S13, the processing proceeds to step S14, the operation illustrated in the expression (5) is performed to obtain the message v_(i) as a decoding result to be finally output and the message v_(i) is output, and the decoding processing for the LDPC code is terminated.

$\begin{matrix} \left\lbrack {{Math}.\mspace{9mu} 5} \right\rbrack & \; \\ {v_{i} = {u_{0\; i} + {\underset{j = 1}{\sum\limits^{d_{v}}}u_{j}}}} & (5) \end{matrix}$

Here, the operation in the expression (5) is performed using messages u_(j) from all the edges connected to the variable node, differently from the variable node operation in the expression (1).

FIG. 3 is a diagram illustrating an example of the parity check matrix H of a (3, 6) LDPC code (a coding rate of 1/2 and a code length of 12).

In the parity check matrix H in FIG. 3, as in FIG. 1, the column weight is 3 and the row weight is 6.

FIG. 4 is a diagram illustrating a Tanner graph of the parity check matrix H in FIG. 3.

Here, in FIG. 4, the check node is represented by plus “+”, and the variable node is represented by equal “=”. The check node and variable node correspond to a row and a column of the parity check matrix H, respectively. A connection between the check node and the variable node is an edge and corresponds to “1” of an element of the parity check matrix.

In other words, in a case where an element of the j-th row and the i-th column of the parity check matrix is 1, the i-th variable node from the top (“=” node) and the j-th check node from the top (“+” node) are connected by an edge in FIG. 4. The edge indicates that a code bit corresponding to the variable node has a constraint corresponding to the check node.

In a sum product algorithm that is a decoding method of an LDPC code, the variable node operation and the check node operation are repeatedly performed.

FIG. 5 is a diagram illustrating the variable node operation performed in the variable node.

In the variable node, the message v_(i) corresponding to the edge to be calculated is obtained by the variable node operation in the expression (1) using messages u₁ and u₂ from the remaining edges connected to the variable node and the received value u_(0i). Messages corresponding to other edges are similarly obtained.

FIG. 6 is a diagram illustrating the check node operation performed in the check node.

Here, the check node operation in the expression (2) can be rewritten to the expression (6), using a relationship of an expression a×b=exp{ln(|a|)+ln(|b|)}×sign (a)×sign (b). Note that sign (x) is 1 when x≥0 and −1 when x<0.

[Math.  6] $\begin{matrix} \begin{matrix} {u_{j} = {2{\tanh^{- 1}\left( {\prod\limits_{i = 1}^{d_{c} - 1}{\tanh\left( \frac{v_{i}}{2} \right)}} \right)}}} \\ {= {2{\tanh^{- 1}\left\lbrack {\exp\left\{ {\sum\limits_{i = 1}^{d_{c} - 1}{\ln\left( {{\tanh\left( \frac{v_{i}}{2} \right)}} \right)}} \right\} \times {\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( {\tanh\left( \frac{v_{i}}{2} \right)} \right)}}} \right\rbrack}}} \\ {= {2{\tanh^{- 1}\left\lbrack {\exp\left\{ {- \left( {\sum\limits_{i = 1}^{d_{c} - 1}{{- \ln}\;\left( {\tanh\left( \frac{v_{i}}{2} \right)} \right)}} \right)} \right\}} \right\rbrack} \times {\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( v_{i} \right)}}}} \end{matrix} & (6) \end{matrix}$

When the function φ(x) is defined as an expression φ(x)=ln(tan h(x/2)) when x≥0, an expression φ⁻¹(x)=2 tan h⁻¹(e^(−x)) holds and thus the expression (6) can be deformed into the expression (7).

$\begin{matrix} \left\lbrack {{Math}.\mspace{14mu} 7} \right\rbrack & \; \\ {u_{j} = {{\phi^{- 1}\left( {\sum\limits_{i = 1}^{d_{c} - 1}{\phi\left( {v_{i}} \right)}} \right)} \times {\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( v_{i} \right)}}}} & (7) \end{matrix}$

In the check node, the check node operation in the expression (2) is performed according to the expression (7).

In other words, in the check node, the message u_(j) corresponding to the edge to be calculated is obtained by the check node operation in the expression (7) using messages v₁, v₂, v₃, v₄, and v₅ from the remaining edges connected to the check node, as illustrated in FIG. 6.

Messages corresponding to other edges are similarly obtained.

Note that the function φ(x) in the expression (7) can be expressed by the expression φ(x)=ln((e^(x)+1)/(e^(x)−1)), and φ(x)=φ⁻¹(x) holds when x>0. When the functions φ(x) and φ⁻¹(x) are implemented in hardware, the functions may be implemented using look up tables (LUTs), and the LUTs are the same.

Configuration Example of Transmission System to Which Present Technology is Applied

FIG. 7 is a diagram illustrating a configuration example of an embodiment of a transmission system (a system refers to a group of a plurality of logically gathered devices, and whether or not the devices of configurations are in the same casing is irrelevant) to which the present technology is applied.

The transmission system in FIG. 7 is configured by a transmission device 11 and a reception device 12.

The transmission device 11 performs transmission (broadcasting) of, for example, a television broadcast program or the like. In other words, the transmission device 11 encodes target data to be transmitted, such as image data and audio data as a program, into an LDPC code, and transmits the LDPC code via a communication path 13 such as a satellite line, a ground wave, or a cable (wired line), for example.

The reception device 12 receives the LDPC code transmitted from the transmission device 11 via the communication path 13, decodes the LDPC code to the target data, and outputs the target data.

Here, it is known that the LDPC code used in the transmission system in FIG. 7 exhibits extremely high capability in an additive white Gaussian noise (AWGN) communication path.

Meanwhile, in the communication path 13, burst errors and erasures may occur. For example, in particular, in a case where the communication path 13 is a ground wave, power of a certain symbol becomes zero (erasure) in some cases according to a delay of an echo (a path other than a main path) in a multipath environment where a desired to undesired ratio (D/U) is 0 dB (power of undesired=echo is equal to power of desired=main path) in an orthogonal frequency division multiplexing (OFDM) system.

Furthermore, power of the entire symbols of OFDM at a specific time may become zero (erasure) due to a Doppler frequency in the case where D/U is 0 dB even in a flutter (a communication path in which a delay is 0 and to which an echo with Doppler frequency is added).

Moreover, a burst error may occur due to a wiring condition from a receiving unit (not illustrated) on the reception device 12 side such as an antenna that receives a signal from the transmission device 11 to the reception device 12, or power supply instability of the reception device 12.

Meanwhile, in decoding the LDPC code, the variable node operation in the expression (1) with addition of (the received value u_(0i) of) the code bit of the LDPC code is performed, as illustrated in FIG. 5, at a column of the parity check matrix H and thus at the variable node corresponding to the code bit of the LDPC code. Therefore, if an error occurs in the code bit used in the variable node operation, the accuracy of an obtained message decreases.

Then, in decoding the LDPC code, the check node operation in the expression (7) is performed in the check node using the messages obtained at the variable nodes connected to the check node. Therefore, if the number of check nodes in which (the code bits of the LDPC codes corresponding to) a plurality of connected variable nodes becomes error (including erasure) at the same time is large, the performance of the decoding deteriorates.

In other words, for example, if two or more of the variable nodes connected to the check node become erasures at the same time, for example, the check node returns a message informing that a probability of a value being 0 and a probability of a value being 1 are equal to all the variable nodes. In this case, the check node returning the equal probability message will not contribute to one decoding processing (a set of the variable node operation and the check node operation). As a result, a large number of repetitions of the decoding processing is required, resulting in deterioration of the performance of the decoding and an increase in the power consumption of the reception device 12 for decoding the LDPC code.

Therefore, in the transmission system in FIG. 7, improvement of resistance to burst errors and erasure is possible while maintaining the performance in the AWGN communication path (AWGN channel).

Configuration Example of Transmission Device 11

FIG. 8 is a block diagram illustrating a configuration example of the transmission device 11 in FIG. 7.

In the transmission device 11, one or more input streams as the target data are supplied to a mode adaptation/multiplexer 111.

The mode adaptation/multiplexer 111 performs processing such as mode selection and multiplexing of the one or more input streams supplied thereto as necessary, and supplies resulting data to a padder 112.

The padder 112 performs necessary zero padding (insertion of null) to the data from the mode adaptation/multiplexer 111, and supplies resulting data to a base band (BB) scrambler 113.

The BB scrambler 113 applies BB scramble to the data from the padder 112, and supplies resulting data to a BCH encoder 114.

The BCH encoder 114 performs BCH coding for the data from the BB scrambler 113, and supplies resultant data to an LDPC encoder 115 as LDPC target data to be LDPC encoded.

The LDPC encoder 115 (encoding unit) performs, for the LDPC target data from the BCH encoder 114, LDPC coding according to a parity check matrix and the like in which a parity matrix that is a portion corresponding to a parity bit of the LDPC code has a step (dual diagonal) structure, and outputs an LDPC code having the LDPC target data as information bits, for example.

In other words, the LDPC encoder 115 performs LDPC coding for coding the LDPC target data to an LDPC code (corresponding to the parity check matrix) defined in a predetermined standard such as DVB-S.2, DVB-T.2, DVB-C.2, or ATSC 3.0 or to another LDPC code, for example, and outputs a resulting LDPC code.

Here, the LDPC code defined in the standard of DVB-S.2 or ATSC 3.0 is an irregular repeat accumulate (IRA) code, and (a part or all of) the parity matrix in the parity check matrix of the LDPC code has a step structure. The parity matrix and the step structure will be described below. Furthermore, the IRA code is described in, for example, “Irregular Repeat-Accumulate Codes,” H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, September 2000.

The LDPC code output by the LDPC encoder 115 is supplied to a bit interleaver 116.

The bit interleaver 116 performs bit interleaving described below for the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the bit interleaving to a mapper (Mapper) 117.

The mapper 117 maps the LDPC code from the bit interleaver 116 to a signal point representing one symbol of quadrature modulation in units of code bits of one bit or more (in units of symbols) of the LDPC code and performs quadrature modulation (multiple value modulation).

In other words, the mapper 117 maps the LDPC code from the bit interleaver 116 into signal points determined by a modulation method for performing the quadrature modulation of an LDPC code, on a constellation that is an IQ plane defined with an I axis representing an I component in phase with a carrier and a Q axis representing a Q component orthogonal to the carrier, and performs the quadrature modulation.

In a case where the number of constellation signal points used in the modulation method of the quadrature modulation performed by the mapper 117 is 2^(m), the mapper 117 maps the LDPC code from the bit interleaver 116 into signal points representing symbols, of 2^(m) signal points, in units of symbols, where m-bit code bits of the LDPC code are a symbol (one symbol).

Here, examples of the modulation method of the quadrature modulation performed by the mapper 117 include the modulation method defined in the standard such as DVB-S.2 or ATSC 3.0, and other modulation methods, in other words, for example, binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), phase-shift keying (8PSK), amplitude phase-shift keying (16APSK), 32APSK, quadrature amplitude modulation (16QAM), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, and pulse amplitude modulation (4PAM). Which modulation method of the quadrature modulation is used in the mapper 117 is set in advance according to an operation of an operator of the transmission device 11, for example.

Data obtained by the processing in the mapper 117 (the mapping result of mapped symbols at the signal points) is supplied to a time interleaver 118.

The time interleaver 118 performs time interleaving (interleaving in a time direction) in units of symbols, for the data from the mapper 117, and supplies resulting data to a single input single output/multiple input single output encoder (SISO/MISO encoder) 119.

The SISO/MISO encoder 119 applies space-time coding to the data from the time interleaver 118, and supplies the data to a frequency interleaver 120.

The frequency interleaver 120 performs frequency interleaving (interleaving in a frequency direction) in units of symbols, for the data from the SISO/MISO encoder 119, and supplies the data to a frame builder/resource allocation unit 131.

Meanwhile, control data (signalling) for transmission control such as base band (BB) signalling (BB header) is supplied to a BCH encoder 121, for example.

The BCH encoder 121 performs BCH coding for the control data supplied thereto, similarly to the BCH encoder 114, and supplies resulting data to an LDPC encoder 122.

The LDPC encoder 122 performs LDPC coding for the data from the BCH encoder 121 as LDPC target data, similarly to the LDPC encoder 115, and supplies a resulting LDPC code to a mapper 123.

The mapper 123 maps the LDPC code from the LDPC encoder 122 to a signal point representing one symbol of quadrature modulation in units of code bits of one bit or more (in units of symbols) of the LDPC code and performs quadrature modulation, similarly to the mapper 117, and supplies resulting data to a frequency interleaver 124.

The frequency interleaver 124 performs frequency interleaving in in units of symbols, for the data from the mapper 123, similarly to the frequency interleaver 120, and supplies resulting data to a frame builder/resource allocation unit 131.

The frame builder/resource allocation unit 131 inserts pilot symbols into necessary positions of the data (symbols) from the frequency interleavers 120 and 124, and configures a frame by a predetermined number of symbols (for example, a physical layer (PL) frame, a T2 frame, a C2 frame, or the like) from resulting data (symbols), and supplies the frame to an OFDM generation unit 132.

The OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame builder/resource allocation unit 131, and transmits the OFDM signal via the communication path 13 (FIG. 7).

Note that the transmission device 11 can be configured without including part of the blocks illustrated in FIG. 8, such as the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, for example.

Configuration Example of Bit Interleaver 116

FIG. 9 is a block diagram illustrating a configuration example of the bit interleaver 116 in FIG. 8.

The bit interleaver 116 has a function to interleave data, and is configured by a parity interleaver 23, a group-wise interleaver 24, and a block interleaver 25.

The parity interleaver 23 performs parity interleaving to interleave the position of another parity bit with the parity bit of the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

The group-wise interleaver 24 performs group-wise interleaving for the LDPC code from the parity interleaver 23, and supplies the LDPC code after the group-wise interleaving to the block interleaver 25.

Here, in the group-wise interleaving, the LDPC code from the parity interleaver 23 is interleaved in units of bit groups, where 360 bits of one section is set as a bit group, the one section being obtained by dividing the LDPC code of one code from the head of the LDPC code into sections in units of 360 bits, the unit being equal to a parallel factor P to be described below, and taking one of the divided sections as the one section.

In a case of performing the group-wise interleaving, an error rate can be improved as compared with a case of not performing the group-wise interleaving. As a result, favorable communication quality can be secured in data transmission.

The block interleaver 25 performs block interleaving for demultiplexing the LDPC code from the group-wise interleaver 24 to symbolize the LDPC code of one code into an m-bit symbol that is a unit of mapping, and supplies the symbol to the mapper 117 (FIG. 8), for example.

Here, in the block interleaving, for example, the LDPC code from the group-wise interleaver 24 is written in a column (vertical) direction and is read in a row (cross) direction with respect to a storage region in which columns as storage regions each storing a predetermined bit length in the column direction are arranged in the row direction by the number of bit length m of the symbol, whereby the LDPC code is symbolized into the m-bit symbol.

<Parity Check Matrix of LDPC Code>

FIG. 10 is a diagram illustrating an example of the parity check matrix H used for LDPC coding in the LDPC encoder 115 in FIG. 8.

The parity check matrix H has a low-density generation matrix (LDGM) structure and can be expressed as an expression H=[H_(A)|H_(T)] (elements of the information matrix H_(A) are on the left side and elements of the parity matrix H_(T) are on the right side) using an information matrix H_(A) of a portion corresponding to the information bits and a parity matrix H_(T) corresponding to the parity bits, of the code bits of the LDPC code.

Here, the bit length of the information bits and the bit length of the parity bits, of the code bits of the LDPC code of one code (one codeword), are respectively referred to as an information length K and a parity length M, and the bit length of the code bits of one (one codeword) LDPC code is referred to as code length N (=K+M).

The information length K and the parity length M of the LDPC code of a given code length N are determined by a coding rate. Furthermore, the parity check matrix H is a matrix of M×N in rows×columns (M-row N-column matrix). Then, the information matrix H_(A) is an M×K matrix, and the parity matrix H_(T) is an M×M matrix.

FIG. 11 is a diagram illustrating an example of the parity matrix H_(T) of the parity check matrix H used for LDPC coding in the LDPC encoder 115 in FIG. 8.

As the parity matrix H_(T) of the parity check matrix H used for LDPC coding in the LDPC encoder 115, a parity matrix H_(T) similar to the parity check matrix H of the LDPC code defined in the standard such as DVB-T.2 can be adopted, for example.

The parity matrix H_(T) of the parity check matrix H of the LDPC code defined in the standard such as DVB-T.2 is a matrix having a step structure (lower bidiagonal matrix) in which elements of 1 are arranged in a step-like manner, as illustrated in FIG. 11. The row weight of the parity matrix H_(T) is 1 in the 1st row and 2 in all the remaining rows. Furthermore, the column weight is 1 in the last one column and 2 in all the remaining columns.

As described above, the LDPC code of the parity check matrix H in which the parity matrix H_(T) has the step structure can be easily generated using the parity matrix H.

In other words, the LDPC code (one codeword) is expressed with a row vector c, and a column vector obtained by transposing the row vector thereof is represented as c^(T). Furthermore, a portion of the information bits, of the row vector c that is the LDPC code, is expressed with a row vector A, and a portion of the parity bits, of the row vector c, is expressed with a row vector T.

In this case, the row vector c can be expressed as an expression c=[A|T] (elements of the row vector A are on the left side and elements of the row vector T are on the right side) using the row vector A as the information bits and the row vector T as the parity bits.

The parity check matrix H and the row vector c=[A|T] as the LDPC code need to satisfy an expression Hc^(T)=0, and the row vector T as the parity bits constituting the row vector c=[A|T] satisfying the expression Hc^(T)=0 can be sequentially obtained (in order) by sequentially setting the element of each row to 0 from the element in the 1st row of the column vector Hc^(T) in the expression Hc^(T)=0 in a case where the parity matrix H_(T) of the parity check matrix H=[H_(A)|H_(T)] has the step structure illustrated in FIG. 11.

FIG. 12 is a diagram for describing the parity check matrix H of the LDPC code defined in the standard such as DVB-T.2.

In the parity check matrix H of the LDPC code defined in the standard such as DVB-T.2, the column weight is X in KX columns from the 1st column, 3 in following K3 columns, 2 in following M−1 columns, and 1 in the last one column.

Here, KX+K3+M−1+1 is equal to the code length N.

FIG. 13 is a diagram illustrating the numbers of columns KX, K3, and M, and the column weight X for each coding rate r of the LDPC code defined in the standard such as DVB-T.2.

In the standard such as DVB-T.2, LDPC codes having code lengths N of 64800 bits and 16200 bits are defined.

Then, eleven coding rates (nominal rates) of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined for the LDPC code with the code length N of 64800 bits. Ten coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined for the LDPC code with the code length N of 16200 bits.

Here, the code length N of 64800 bits is also referred to as 64k bits and the code length N of 16200 bits is also referred to as 16k bits.

In regard to the LDPC code, code bits corresponding to a column having a larger column weight of the parity check matrix H tend to have a lower error rate.

In the parity check matrix H defined in the standard such as DVB-T.2 illustrated in FIGS. 12 and 13, the column weight tends to be larger in columns on the head side (left side), and therefore the code bits on the head side tend to be more resistant to errors and end code bits tend to be more susceptible to errors in the LDPC code corresponding to the parity check matrix H.

<Parity Interleaving>

The parity interleaving by the parity interleaver 23 in FIG. 9 will be described with reference to FIGS. 14 to 16.

FIG. 14 is a diagram illustrating an example of (a part of) a Tanner graph of the parity check matrix of the LDPC code.

As illustrated in FIG. 14, when two or more of (the code bits corresponding to) the variable nodes connected to the check node become errors such as erasures at the same time, the check node returns a message informing that a probability of a value being 0 and a probability of a value being 1 are equal to all the variable nodes connected to the check node. Therefore, if a plurality of variable nodes connected to the same check node becomes erasures or the like at the same time, the performance of the decoding will deteriorate.

By the way, the LDPC code output from the LDPC encoder 115 in FIG. 8 is an IRA code, similarly to the LDPC code defined in the standard such as DVB-T.2, for example, and the parity matrix H_(T) of the parity check matrix H has a step structure, as illustrated in FIG. 11.

FIG. 15 is a diagram illustrating examples of the parity matrix H_(T) having the step structure, as illustrated in FIG. 11, and a Tanner graph corresponding to the parity matrix H_(T).

A in FIG. 15 illustrates an example of the parity matrix H_(T) having a step structure, and B in FIG. 15 illustrates a Tanner graph corresponding to the parity matrix H_(T) in A in FIG. 15.

In the parity matrix H_(T) having a step structure, elements of 1 are adjacent (except the 1st row) in rows. Therefore, in the Tanner graph of the parity matrix H_(T), two adjacent variable nodes corresponding to columns of the two adjacent elements where values of the parity matrix H_(T) are 1 are connected to the same check node.

Therefore, when the parity bits corresponding to the above two adjacent variable nodes become errors at the same time due to burst errors, erasures, or the like, the check node connected to the two variable nodes corresponding to the two error parity bits (variable nodes seeking a message using the parity bits) returns the message informing that a probability of a value being 0 and a probability of a value being 1 are equal to the variable nodes connected to the check node. Therefore, the performance of the decoding deteriorates. Then, when a burst length (the bit length of the parity bits that become error in succession) becomes large, the number of check nodes returning the message of equal probability increases, and the performance of the decoding further deteriorates.

Therefore, the parity interleaver 23 (FIG. 9) performs parity interleaving to interleave the positions of other parity bits with the parity bits of the LDPC code from the LDPC encoder 115 in order to prevent deterioration of the performance of the decoding.

FIG. 16 is a diagram illustrating the parity matrix H_(T) of the parity check matrix H corresponding to the LDPC code after the parity interleaving performed by the parity interleaver 23 in FIG. 9.

Here, the information matrix H_(A) of the parity check matrix H corresponding to the LDPC code output by the LDPC encoder 115 has a cyclic structure, similarly to the information matrix of the parity check matrix H corresponding to the LDPC code defined in the standard such as DVB-T.2.

The cyclic structure is a structure in which a certain column matches a cyclically shifted another column, and includes, for example, a structure in which, for each P columns, positions of 1 of rows of the P columns become positions cyclically shifted in the column direction by a predetermined value such as a value proportional to a value q obtained by dividing the first column of the P columns by the parity length M. Hereinafter, the P columns in the cyclic structure are referred to as a parallel factor, as appropriate.

As the LDPC code defined in the standard such as DVB-T.2, there are two types of LDPC codes with the code lengths N of 64800 bits and 16200 bits as described in FIGS. 12 and 13. For both the two types of LDPC codes, the parallel factor P is defined as 360, which is one of divisors of the parity length M except 1 and M.

Furthermore, the parity length M is a value other than a prime number represented by an expression M=q×p=q×360, using a value q that varies depending on the coding rate. Therefore, similarly to the parallel factor P, the value q is also another one of the divisors of the parity length M except 1 and M, and is obtained by dividing the parity length M by the parallel factor P (a product of P and q, which are the divisors of the parity length M, becomes the parity length M).

As described above, the parity interleaver 23 interleaves the position of (K+Py+x+1)th code bit with (K+qx+y+1)th code bit of code bits of an N-bit LDPC code, as the parity interleaving, where the information length is K, an integer from 0 to P, exclusive of P, is x, and an integer from 0 to q, exclusive of q, is y.

Since both the (K+qx+y+1)th code bit and the (K+Py+x+1)th code bit are subsequent code bits of (K+1)th code bit and thus are parity bits, the positions of the parity bits of the LDPC code are moved according to the parity interleaving.

According to such parity interleaving, (the parity bits corresponding to) the variable nodes connected to the same check node are separated by the parallel factor P, in other words, 360 bits. Therefore, in a case where the burst length is less than 360 bits, a situation where a plurality of variable nodes connected to the same check node becomes error at the same time can be avoided, and as a result, the resistance to the burst errors can be improved.

Note that the LDPC code after the parity interleaving to interleave the position of the (K+Py+x+1)th code bit with the (K+qx+y+1)th code bit matches the LDPC code of the parity check matrix (hereinafter also referred to as a transformed parity check matrix) that is obtained by performing column permutation to permutate the (K+qx+y+1)th column of the original parity check matrix H with the (K+Py+x+1)th column.

Furthermore, a pseudo cyclic structure having P columns (360 columns in FIG. 16) as a unit appears in the parity matrix of the transformed parity check matrix, as illustrated in FIG. 16.

Here, the pseudo cyclic structure means a structure having a cyclic structure excluding a part.

A transformed parity check matrix obtained by applying column permutation corresponding to the parity interleaving to the parity check matrix of the LDPC code defined in the standard such as DVB-T.2 lacks one element of 1 (has an element of 0) in a portion (a shift matrix to be described below) of 360 rows×360 columns in an upper right corner portion of the transformed parity check matrix, and thus has a so-called pseudo cyclic structure, rather than a (complete) cyclic structure on that regard.

A transformed parity check matrix for the parity check matrix of the LDPC code output by the LDPC encoder 115 has a pseudo cyclic structure, similarly to the transformed parity check matrix for the parity check matrix of the LDPC code defined in the standard such as DVB-T.2, for example.

Note that the transformed parity check matrix in FIG. 16 is a matrix obtained by applying the column permutation corresponding to the parity interleaving to the original parity check matrix H, and applying permutation for rows (row permutation) so as to configure the transformed parity check with configuration matrices to be described below.

FIG. 17 is a flowchart for describing processing performed by the LDPC encoder 115, the bit interleaver 116, and the mapper 117 in FIG. 8.

The LDPC encoder 115 waits for supply of the LDPC target data from the BCH encoder 114. In step S101, the LDPC encoder 115 encodes the LDPC target data into the LDPC code, and supplies the LDPC code to the bit interleaver 116. The processing proceeds to step S102.

In step S102, the bit interleaver 116 performs the bit interleaving for the LDPC code from the LDPC encoder 115, and supplies the symbol obtained by the bit interleaving to the mapper 117. The processing proceeds to step S103.

In other words, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs the parity interleaving for the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

The group-wise interleaver 24 performs the group-wise interleaving for the LDPC code from the parity interleaver 23, and supplies the LDPC code to the block interleaver 25.

The block interleaver 25 performs the block interleaving for the LDPC code after the group-wise interleaving by the group-wise interleaver 24, and supplies a resulting m-bit symbol to the mapper 117.

In step S103, the mapper 117 maps the symbol from the block interleaver 25 to any of 2^(m) signal points determined by the modulation method of the quadrature modulation performed by the mapper 117 and performs the quadrature modulation, and supplies resulting data to the time interleaver 118.

As described above, by performing the parity interleaving and the group-wise interleaving, the error rate of the case where a plurality of code bits of the LDPC code is transmitted as one symbol can be improved.

Here, in FIG. 9, for convenience of description, the parity interleaver 23 as a block for performing the parity interleaving and the group-wise interleaver 24 as a block for performing the group-wise interleaving are separately configured. However, the parity interleaver 23 and the group-wise interleaver 24 can be integrally configured.

In other words, both the parity interleaving and the group-wise interleaving can be performed by writing and reading code bits with respect to a memory, and can be expressed by a matrix for converting an address for writing code bits (write address) into an address for reading code bits (read address).

Therefore, by obtaining a matrix obtained by multiplying a matrix expressing the parity interleaving and a matrix expressing the group-wise interleaving, the parity interleaving is performed by converting code bits by these matrices, and further the group-wise interleaving is performed for the LDPC code after the parity interleaving, whereby a result can be obtained.

Furthermore, the block interleaver 25 can also be integrally configured in addition to the parity interleaver 23 and the group-wise interleaver 24

In other words, the block interleaving performed by the block interleaver 25 can also be expressed by the matrix converting the write address of the memory for storing the LDPC code into the read address.

Therefore, by obtaining a matrix obtained by multiplying the matrix expressing the parity interleaving, the matrix expressing the group-wise interleaving, and the matrix expressing the block interleaving, the parity interleaving, the group-wise interleaving, and the block interleaving can be collectively performed by the matrices.

Note that one or the amount of the parity interleaving and the group-wise interleaving may not be performed.

Configuration Example of LDPC Encoder 115

FIG. 18 is a block diagram illustrating a configuration example of the LDPC encoder 115 in FIG. 8.

Note that the LDPC encoder 122 in FIG. 8 is similarly configured.

As described in FIGS. 12 and 13, in the standard such as DVB-T.2, LDPC codes having two types of code lengths N of 64800 bits and 16200 bits are defined.

Then, the eleven coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined for the LDPC code with the code length N of 64800 bits. The ten coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined for the LDPC code with the code length N of 16200 bits (FIGS. 12 and 13).

The LDPC encoder 115 can perform, for example, such coding (error correction coding) of the LDPC codes with the code lengths N of 64800 bits and 16200 bits and the coding rates according to the parity check matrix H prepared for each code length N and each coding rate.

Furthermore, the LDPC encoder 115 can perform LDPC coding according to the parity check matrix H of an LDPC code with a code length N of 17280 bits or another arbitrary code length N and a coding rate of 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, or 14/16 or another arbitrary coding rate r.

The LDPC encoder 115 is configured by a coding processing unit 601 and a storage unit 602.

The coding processing unit 601 is configured by a coding rate setting unit 611, an initial value table reading unit 612, a parity check matrix generation unit 613, an information bit reading unit 614, a coding parity operation unit 615, and a control unit 616. The coding processing unit 601 performs the LDPC coding for the LDPC target data supplied to the LDPC encoder 115, and supplies a resulting LDPC code to the bit interleaver 116 (FIG. 8).

In other words, the coding rate setting unit 611 sets the code length N and the coding rate r of the LDPC code, and in addition, specific information specifying the LDPC code, according to the operation of the operator, for example.

The initial value table reading unit 612 reads, from the storage unit 602, a parity check matrix initial value table to be described below, expressing the parity check matrix of the LDPC code specified with the specific information set by the coding rate setting unit 611.

The parity check matrix generation unit 613 generates the parity check matrix H on the basis of the parity check matrix initial value table read by the initial value table reading unit 612, and stores the parity check matrix H in the storage unit 602. For example, the parity check matrix generation unit 613 arranges the elements of 1 of the information matrix H_(A) corresponding to the information length K (=the code length N−the parity length M) according to the code length N and the coding rate r set by the coding rate setting unit 611 with a period of every 360 columns (parallel factor P) in the column direction to generate the parity check matrix H, and stores the parity check matrix H in the storage unit 602.

The information bit reading unit 614 reads (extracts) the information bits of the information length K from the LDPC target data supplied to the LDPC encoder 115.

The coding parity operation unit 615 reads the parity check matrix H generated by the parity check matrix generation unit 613 from the storage unit 602, and calculates the parity bits for the information bits read by the information bit reading unit 614 on the basis of a predetermined expression using the parity check matrix H, thereby generating the codeword (LDPC code).

The control unit 616 controls the blocks constituting the coding processing unit 601.

The storage unit 602 stores, for example, a plurality of parity check matrix initial value tables respectively corresponding to the plurality of coding rates and the like illustrated in FIGS. 12 and 13 for the respective code lengths N such as 64800 bits and 16200 bits, parity check matrix initial value tables respectively corresponding to the coding rates of 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 for the code length N of 17280 bits, and a parity check matrix initial value table of the parity check matrix H of the LDPC code with an arbitrary code length N and an arbitrary coding rate r. Furthermore, the storage unit 602 temporarily stores data necessary for the processing of the coding processing unit 601.

FIG. 19 is a flowchart for describing an example of the processing of the LDPC encoder 115 in FIG. 18.

In step S201, the coding rate setting unit 611 sets the code length N and the coding rate r for performing the LDPC coding, and in addition, the specific information specifying the LDPC code.

In step S202, the initial value table reading unit 612 reads, from the storage unit 602, the predetermined parity check matrix initial value table specified with the code length N, the coding rate r, and the like as the specific information set by the coding rate setting unit 611.

In step S203, the parity check matrix generation unit 613 obtains (generates) the parity check matrix H of the LDPC code with the code length N and the coding rate r set by the coding rate setting unit 611, using the parity check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612, and supplies and stores the parity check matrix H in the storage unit 602.

In step S204, the information bit reading unit 614 reads the information bits of the information length K (=N×r) corresponding to the code length N and the coding rate r set by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115, and reads the parity check matrix H obtained by the parity check matrix generation unit 613 from the storage unit 602, and supplies the information bits and the parity check matrix H to the coding parity operation unit 615.

In step S205, the coding parity operation unit 615 sequentially operates the parity bit of the codeword c that satisfies the expression (8), using the information bits and the parity check matrix H from the information bit reading unit 614. Hc ^(T)=0  (8)

In the expression (8), c represents the row vector as the codeword (LDPC code), and c^(T) represents transposition of the row vector c.

Here, as described above, in the case of expressing the portion of the information bits, of the row vector c as the LDPC code (one codeword), with the row vector A, and the portion of the parity bits, of the row vector c, with the row vector T, the row vector c can be expressed as the expression c=[A|T] using the row vector A as the information bits and the row vector T as the parity bits.

The parity check matrix H and the row vector c=[A|T] as the LDPC code need to satisfy the expression Hc^(T)=0, and the row vector T as the parity bits constituting the row vector c=[A|^(T)] satisfying the expression Hc^(T)=0 can be sequentially obtained by sequentially setting the element of each row to 0 from the element in the 1st row of the column vector Hc^(T) in the expression Hc^(T)=0 in the case where the parity matrix H_(T) of the parity check matrix H=[H_(A)|H_(T)] has the step structure illustrated in FIG. 11.

The coding parity operation unit 615 obtains the parity bits T for the information bits A from the information bit reading unit 614, and outputs the codeword c=[A|T] expressed with the information bits A and the parity bits T as an LDPC coding result of the information bits A.

Thereafter, in step S206, the control unit 616 determines whether or not to terminate the LDPC coding. In a case where it is determined in step S206 that the LDPC coding is not terminated, in other words, in a case where there is still LDPC target data to be LDPC-encoded, the processing returns to step S201 (or step S204), and hereinafter the processing from step S201 (or step S204) to step S206 is repeated, for example.

Furthermore, in step S206, in a case where it is determined that the LDPC coding is terminated, in other words, for example, in a case where there is no LDPC target data to be LDPC-encoded, the LDPC encoder 115 terminates the processing.

In regard to the LDPC encoder 115, the parity check matrix initial value table (expressing the parity check matrix) of the LDPC codes of various code lengths N and coding rates r can be prepared in advance. The LDPC encoder 115 can perform the LDPC coding for the LDPC codes of various code lengths N and coding rates r, using the parity check matrix H generated from the parity check matrix initial value table prepared in advance.

Example of Parity Check Matrix Initial Value Table

For example, the parity check matrix initial value table is a table representing the positions of the elements of 1 of the information matrix H_(A) (FIG. 10) corresponding to the information length K according to the code length N and the coding rate r of the LDPC code (the LDPC code defined by the parity check matrix H) of the parity check matrix H in every 360 columns (parallel factor P), and is created in advance for each parity check matrix H of each code length N and each coding rate r.

In other words, the parity check matrix initial value table represents at least the positions of the elements of 1 of the information matrix H_(A) in every 360 columns (parallel factor P).

Furthermore, as the parity check matrix H, there are a parity check matrix in which the entire parity matrix H_(T) has a step structure, and a parity check matrix in which a part of the parity matrix H_(T) has a step structure and the remaining part is a diagonal matrix (identity matrix).

Hereinafter, an expression method for the parity check matrix initial value table representing the parity check matrix in which a part of the parity matrix H_(T) has a step structure and the remaining part is a diagonal matrix is also referred to as type A method. Furthermore, an expression method for the parity check matrix initial value table representing the parity check matrix in which the entire parity matrix H_(T) has a step structure is also referred to as type B method.

Furthermore, the LDPC code for the parity check matrix represented by the parity check matrix initial value table by the type A method is also referred to as type A code, and the LDPC code for the parity check matrix represented by the parity check matrix initial value table by the type B method is also referred to as type B code.

The designations “type A” and “type B” are designations in accordance with the standard of ATSC 3.0. For example, in ATSC 3.0, both the type A code and type B code are adopted.

Note that, in DVB-T.2 and the like, the type B code is adopted.

FIG. 20 is a diagram illustrating an example of the parity check matrix initial value table by the type B method.

In other words, FIG. 20 illustrates the parity check matrix initial value table (representing the parity check matrix H) of the type B code with the code length N of 16200 bits and the coding rate r (coding rate on the notation of DVB-T.2) of 1/4 defined in the standard of DVB-T.2.

The parity check matrix generation unit 613 (FIG. 18) obtains the parity check matrix H as follows using the parity check matrix initial value table by the type B method.

FIG. 21 is a diagram for describing a method of obtaining the parity check matrix H from the parity check matrix initial value table by the type B method.

In other words, FIG. 21 illustrates the parity check matrix initial value table of the type B code with the code length N of 16200 bits and the coding rate r of 2/3 defined in the standard of DVB-T.2.

The parity check matrix initial value table by the type B method is a table representing the positions of the elements of 1 of the entire information matrix H_(A) corresponding to the information length K according to the code length N and the coding rate r of the LDPC code in every 360 columns (parallel factor P). In the i-th row, row numbers of the elements of 1 of the (1+360×(i−1))th column of the parity check matrix H (row numbers of when the row number of the 1st row of the parity check matrix H is counted as 0) are arranged by the number of the column weights of the (1+360×(i−1))th column.

Here, since the parity matrix H_(T) (FIG. 10) corresponding to the parity length M of the parity check matrix H by the type B method has the step structure as illustrated in FIG. 15, the parity check matrix H can be obtained if the information matrix H_(A) (FIG. 10) corresponding to the information length K can be obtained according to the parity check matrix initial value table.

The number of rows k+1 of the parity check matrix initial value table by the type B method differs depending on the information length K.

The relationship of the expression (9) holds between the information length K and the number of rows k+1 of the parity check matrix initial value table. K=(k+1)×360  (9)

Here, 360 in the expression (9) is the parallel factor P described in FIG. 16.

In the parity check matrix initial value table in FIG. 21, thirteen numerical values are arranged in the 1st to 3rd rows, and three numerical values are arranged in the 4th to (k+1)th rows (30th row in FIG. 21).

Therefore, the column weight of the parity check matrix H obtained from the parity check matrix initial value table in FIG. 21 is 13 from the 1st to (1+360×(3−1)−1)th columns, and 3 from the (1+360×(3−1))th to K-th columns.

The 1st row of the parity check matrix initial value table in FIG. 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622, which indicates that, in the 1st column of the parity check matrix H, the elements of the rows with the row numbers of 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are 1 (and the other elements are 0).

Furthermore, the 2nd row of the parity check matrix initial value table in FIG. 21 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, and 3108, which indicates that, in the 361st (=1+360×(2−1))th column of the parity check matrix H, the elements of the rows with the row numbers of 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, and 3108 are 1.

As described above, the parity check matrix initial value table represents the positions of the elements of 1 of the information matrix H_(A) of the parity check matrix H in every 360 columns.

The columns other than the (1+360×(i−1))th column of the parity check matrix H, in other words, the (2+360×(i−1)th to (360×i)th columns are obtained by cyclically shifting and arranging the elements of 1 of the (1+360×(i−1))th column determined by the parity check matrix initial value table downward (downward of the columns) according to the parity length M.

In other words, for example, the (2+360×(i−1))th column is obtained by cyclically shifting the (1+360×(i−1))th column downward by M/360 (=q). The next (3+360×(i−1))th column is obtained by cyclically shifting the (1+360×(i−1))th column downward by 2×M/360 (=2×q) (by cyclically shifting the (2+360×(i−1))th column downward by M/360 (=q)).

Now, in a case where the numerical value of the j-th column (j-th from the left) in the i-th row (i-th from the top) of the parity check matrix initial value table is represented as h_(i,j) and the row number of the element of j-th of 1 of the w-th column of the parity check matrix H is represented as H_(w-j), the row number H_(w-j) of the element of 1 of the w-th column that is a column other than the (1+360×(i−1))th column of the parity check matrix H can be obtained by the expression (10). H _(w-j)=mod{h _(i,j)+mod((w−1),P)×q,M)  (10)

Here, mod (x, y) means the remainder of dividing x by y.

Furthermore, P is the above-described parallel factor, and in the present embodiment, P is 360 as in the standard of DVB-T.2 or the like and ATSC 3.0, for example. Moreover, q is a value M/360 obtained by dividing the parity length M by the parallel factor P (=360).

The parity check matrix generation unit 613 (FIG. 18) specifies the row number of the element of 1 in the (1+360×(i−1))th column of the parity check matrix H using the parity check matrix initial value table.

Moreover, the parity check matrix generation unit 613 (FIG. 18) calculates the row number H_(w-j) of the element of 1 in the w-th column that is a column other than the (1+360×(i−1))th column of the parity check matrix H according to the expression (10), and generates the parity check matrix H in which the elements of the row numbers obtained as described above are 1.

FIG. 22 is a diagram illustrating a structure of the parity check matrix H by the type A method.

The parity check matrix by the type A method is configured by an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

The A matrix is an upper left matrix in the parity check matrix H, of M1 rows and K columns expressed by a predetermined value M1 and the information length K=the code length N×the coding rate r of the LDPC code.

The B matrix is a matrix of M1 rows and M1 columns having a step structure adjacent to the right of the A matrix.

The C matrix is a matrix of N−K−M1 rows and K+M1 columns adjacent to below the A matrix and the B matrix.

The D matrix is an identity matrix of N−K−M1 rows and N−K−M1 columns adjacent to the right of the C matrix.

The Z matrix is a zero matrix (0 matrix) of M1 rows and N−K−M1 columns adjacent to the right of the B matrix.

In the parity check matrix H by the type A method configured by the above A matrix to D matrix and Z matrix, the A matrix and a part of the C matrix constitute the information matrix, and the B matrix, the rest of the C matrix, the D matrix, and the Z matrix constitute the parity matrix.

Note that, since the B matrix is a matrix with a step structure and the D matrix is an identity matrix, a part (the part of the B matrix) of the parity matrix of the parity check matrix H by the type A method has the step structure and the remaining part (the part of the D matrix) is a diagonal matrix (identity matrix).

The A matrix and the C matrix have a cyclic structure of every parallel factor P columns (for example, 360 columns), similarly to the information matrix of the parity check matrix H by type B method, and the parity check matrix initial value table by the type A method represents the positions of the elements of 1 of the A matrix and the C matrix in every 360 columns.

Here, as described above, since the A matrix and a part of the C matrix constitute the information matrix, the parity check matrix initial value table by the type A method representing the positions of the elements of 1 of the A matrix and the C matrix in every 360 columns can be said to represent at least the positions of the elements of 1 of the information matrix in every 360 columns.

Note that, since the parity check matrix initial value table by the type A method represents the positions of the elements of 1 of the A matrix and the C matrix in every 360 columns, the parity check matrix initial value table can also be said to represent the positions of the elements of 1 of a part (the remaining part of the C matrix) of the parity check matrix in every 360 columns.

FIG. 23 is a diagram illustrating an example of the parity check matrix initial value table by the type A method.

In other words, FIG. 23 illustrates an example of the parity check matrix initial value table representing the parity check matrix H with the code length N of 35 bits and the coding rate r of 2/7.

The parity check matrix initial value table by the type A method is a table representing the positions of the elements of 1 of the A matrix and the C matrix in every parallel factor P. In the i-th row, row numbers of the elements of 1 of the (1+P×(i−1))th column of the parity check matrix H (the row numbers of when the row number of the 1st row of the parity check matrix H is counted as 0) are arranged by the number of the column weight of the (1+P×(i−1))th column.

Note that, here, to simplify the description, the parallel factor P is 5, for example.

The parity check matrix H by the type A method has M1, M2, Q1, and Q2 as parameters.

M1 (FIG. 22) is a parameter for determining the size of the B matrix, and takes a value that is a multiple of the parallel factor P. By adjusting M1, the performance of the LDPC code changes, and M1 is adjusted to a predetermined value when determining the parity check matrix H. Here, it is assumed that 15 is adopted as M1, which is three times the parallel factor P=5.

M2 (FIG. 22) takes a value M−M1 obtained by subtracting M1 from the parity length M.

Here, since the information length K is N×r=35×2/7=10 and the parity length M is N−K=35−10=25, M2 is M−M1=25−15=10.

Q1 is obtained according to an expression Q1=M1/P, and represents the number of shifts (the number of rows) of cyclic shift in the A matrix.

In other words, the columns other than the (1+P×(i−1))th column of the A matrix of the parity check matrix H by the type A method, that is, the (2+P×(i−1))th to (P×i)th columns are obtained by cyclically shifting and arranging the elements of 1 of the (1+P×(i−1))th column determined by the parity check matrix initial value table downward (downward of the columns), and Q1 represents the number of shifts of the cyclic shift in the A matrix.

Q2 is obtained according to an expression Q2=M2/P, and represents the number of shifts (the number of rows) of cyclic shift in the C matrix.

In other words, the columns other than the (1+P×(i−1))th column of the C matrix of the parity check matrix H by the type A method, that is, the (2+P×(i−1))th to (P×i)th columns are obtained by cyclically shifting and arranging the elements of 1 of the (1+P×(i−1))th column determined by the parity check matrix initial value table downward (downward of the columns), and Q2 represents the number of shifts of the cyclic shift in the C matrix.

Here, Q1 is M1/P=15/5=3, and Q2 is M2/P=10/5=2.

In the parity check matrix initial value table in FIG. 23, three numerical values are arranged in the 1st and 2nd rows, and one numerical value is arranged in the 3rd to 5th rows. According to the arrangement of the numerical values, the column weights of the A matrix and the C matrix of the parity check matrix H obtained from the parity check matrix initial value table in FIG. 23 are 3 from 1st=(1+5×(1−1))th column to 10th=(5×2)th column, and 1 from the 11th=(1+5×(3−1))th column to 25th=(5×5)th column.

In other words, the 1st row of the parity check matrix initial value table in FIG. 23 is 2, 6, and 18, which represents that, in the 1st column of the parity check matrix H, the elements of the rows with the row numbers of 2, 6, and 18 are 1 (and the other elements are 0).

Here, in this case, since the A matrix (FIG. 22) is a matrix of 15 rows and 10 columns (M1 rows and K columns), and the C matrix (FIG. 22) is a matrix of 10 rows and 25 columns (N−K−M1 rows and K+M1 columns), the rows with the row numbers 0 to 14 of the parity check matrix H are rows of the A matrix, and the rows with the row numbers 15 to 24 of the parity check matrix H are rows of the C matrix.

Therefore, rows #2 and #6 of the rows with the row numbers 2, 6, and 18 (hereinafter described as rows #2, #6, and #18) are rows of the A matrix, and the row #18 is a row of the C matrix.

The 2nd row of the parity check matrix initial value table in FIG. 23 is 2, 10, and 19, which represents that, in the 6th (=(1+5×(2−1))th) column of the parity check matrix H, the elements of the rows #2, #10, and #19 are 1.

Here, in the 6th (=(1+5×(2−1))th) column of the parity check matrix H, the rows #2 and #10 of the rows #2, #10, and #19 are rows of the A matrix, and the row #19 is a row of the C matrix.

The 3rd row of the parity check matrix initial value table in FIG. 23 is 22, which represents that, in the 11th (=(1+5×(3−1))th) column of the parity check matrix H, the element of the row #22 is 1.

Here, the row #22 is a row of the C matrix in the 11th (=(1+5×(3−1))th) column of the parity check matrix H.

Similarly, 19 in the 4th row of the parity check matrix initial value table in FIG. 23 represents that the element of the row #19 is 1 in the 16th (=(1+5×(4−1))th) column of the parity check matrix H. 15 in the fifth row of the parity check matrix initial value table in FIG. 23 represents that the element of the row #15 is 1 in the 21st (=(1+5×(5−1))th) column of the parity check matrix H.

As described above, the parity check matrix initial value table represents the positions of the elements of 1 of the A matrix and the C matrix of the parity check matrix H in every parallel factor P=5 columns.

The columns other than the (1+5×(i−1))th column of the A matrix and the C matrix of the parity check matrix H, that is, the (2+5×(i−1))th to (5×i)th columns are obtained by cyclically shifting and arranging the elements of 1 of the (1+5×(i−1))th column determined by the parity check matrix initial value table downward (downward of the columns) according to the parameters Q1 and Q2.

In other words, for example, the (2+5×(i−1))th column of the A matrix is obtained by cyclically shifting the (1+5×(i−1))th column downward by Q1 (=3). The next (3+5×(i−1))th column is obtained by cyclically shifting the (1+5×(i−1))th column downward by 2×Q1 (=2×3) (by cyclically shifting the (2+5×(i−1))th column downward by Q1).

Furthermore, for example, the (2+5×(i−1))th column of the C matrix is obtained by cyclically shifting the (1+5×(i−1))th column downward by Q2 (=2). The next (3+5×(i−1))th column is obtained by cyclically shifting the (1+5×(i−1))th column downward by 2×Q2 (=2×2) (by cyclically shifting the (2+5×(i−1))th column downward by Q2).

FIG. 24 is a diagram illustrating the A matrix generated from the parity check matrix initial value table in FIG. 23.

In the A matrix in FIG. 24, the elements of the rows #2 and #6 of the 1st (=(1+5×(1−1))th) column are 1 according to the 1st row of the parity check matrix initial value table in FIG. 23.

Then, the columns from the 2nd (=(2+5×(1−1))th) to 5th (=(5+5×(1−1))th) columns are obtained by cyclically shifting the previous columns downward by Q1=3.

Moreover, in the A matrix in FIG. 24, the elements of the rows #2 and #10 of the 6th (=(1+5×(2−1))th) column are 1 according to the 2nd row of the parity check matrix initial value table in FIG. 23.

Then, the columns from the 7th (=(2+5×(2−1))th) to 10th (=(5+5×(2−1))th) columns are obtained by cyclically shifting the previous columns downward by Q1=3.

FIG. 25 is a diagram illustrating parity interleaving of the B matrix.

The parity check matrix generation unit 613 (FIG. 18) generates the A matrix using the parity check matrix initial value table, and arranges the B matrix having a step structure adjacent to the right of the A matrix. Then, the parity check matrix generation unit 613 treats the B matrix as a parity matrix, and performs parity interleaving such that adjacent elements of 1 of the B matrix having step structure are separated in the row direction by the parallel factor P=5.

FIG. 25 illustrates the A matrix and the B matrix after the parity interleaving of the B matrix in FIG. 24.

FIG. 26 is a diagram illustrating the C matrix generated from the parity check matrix initial value table in FIG. 23.

In the C matrix in FIG. 26, the element of the row #18 of the 1st (=(1+5×(1−1))th) column of the parity check matrix H is 1 according to the 1st row of the parity check matrix initial value table in FIG. 23.

Then, the columns from the 2nd (=(2+5×(1−1))th) to 5th (=(5+5×(1−1))th) columns of the C matrix are obtained by cyclically shifting the previous columns downward by Q2=2.

Moreover, in the C matrix in FIG. 26, according to the 2nd to 5th rows of the parity check matrix initial value table in FIG. 23, the elements of the row #19 of the 6th (=(1+5×(2−1))th) column, the row #22 of the 11th (=(1+5×(3−1))th) column, the row #19 of the 16th (=(1+5×(4−1))th) column, and the row #15 of the 21st (=(1+5×(5−1))th) columns, of the parity check matrix H, are 1.

Then, columns from the 7th (=(2+5×(2−−1))th) to the 10th (=(5+5×(2−1))th) columns, columns from the 12th (=(2+5×(3−1))th) to 15th (=(5+5×(3−1))th) columns, columns from the 17th (=(2+5×(4−1))th) to 20th (=(5+5×(4−1))th) columns, and columns from the 22nd (=(2+5×(5−1))th) to the 25th (=(5+5×(5−1))th) columns are obtained by cyclically shifting the previous columns downward by Q2=2.

The parity check matrix generation unit 613 (FIG. 18) generates the C matrix using the parity check matrix initial value table and arranges the C matrix below the A matrix and the B matrix (after parity interleaving).

Moreover, the parity check matrix generation unit 613 arranges the Z matrix adjacent to the right of the B matrix and arranges the D matrix adjacent to the right of the C matrix to generate the parity check matrix H illustrated in FIG. 26.

FIG. 27 is a diagram for describing parity interleaving of the D matrix.

The parity check matrix generation unit 613 treats the D matrix after generating the parity check matrix H in FIG. 26 as a parity matrix, and performs parity interleaving (of only the D matrix) such that the elements of 1 of the odd rows and the next even rows of the D matrix as an identity matrix are separated by the parallel factor P=5 in the row direction.

FIG. 27 illustrates the parity check matrix H after performing the parity interleaving of the D matrix for the parity check matrix H in FIG. 26.

(The coding parity operation unit 615 (FIG. 18) of) the LDPC encoder 115 performs LDPC coding (generates an LDPC code) using the parity check matrix H in FIG. 27, for example.

Here, the LDPC code generated using the parity check matrix H in FIG. 27 is an LDPC code for which parity interleaving has been performed. Therefore, it is not necessary to perform the parity interleaving in the parity interleaver 23 (FIG. 9) for the LDPC code generated using the parity check matrix H in FIG. 27. In other words, the LDPC code generated using the parity check matrix H after the parity interleaving of the D matrix is performed is the LDPC code for which the parity interleaving has been performed. Therefore, the parity interleaving in the parity interleaver 23 is skipped for the LDPC code.

FIG. 28 illustrates a parity check matrix H in which column permutation as parity deinterleaving for restoring the parity interleaving is performed for the B matrix, a part of the C matrix (a portion of the C matrix arranged below the B matrix), and the D matrix of the parity check matrix H in FIG. 27.

The LDPC encoder 115 can perform LDPC coding (generates an LDPC code) using the parity check matrix H in FIG. 28.

In a case of performing the LDPC coding using the parity check matrix H in FIG. 28, an LDPC code for which parity interleaving is not performed can be obtained according to the LDPC coding. Therefore, in a case of performing the LDPC coding using the parity check matrix H in FIG. 28, the parity interleaving is performed in the parity interleaver 23 (FIG. 9).

FIG. 29 is a diagram illustrating a transformed parity check matrix H obtained by performing row permutation for the parity check matrix H in FIG. 27.

The transformed parity check matrix is, as described below, a matrix represented by a combination of a P×P identity matrix, a quasi identity matrix in which one or more of is in the identity matrix are 0, a shift matrix obtained by cyclically shifting the identity matrix or the quasi identity matrix, a sum matrix that is a sum of two or more of the identity matrix, the quasi identity matrix, and the shift matrix, and a P×P zero matrix.

By using the transformed parity check matrix for decoding the LDPC code, architecture of performing P check node operations and variable node operations at the same time can be adopted in decoding the LDPC code, as described below.

<New LDPC Code>

One of methods of securing favorable communication quality in data transmission using an LDPC code, there is a method using an LDPC code with high performance.

Hereinafter, a new LDPC code with high performance (hereinafter also referred to as a new LDPC code) will be described.

As the new LDPC code, for example, the type A code or the type B code corresponding to the parity check matrix H having a cyclic structure with the parallel factor P of 360 similar to that of DVB-T.2, ATSC 3.0, or the like, can be adopted.

The LDPC encoder 115 (FIGS. 8 and 18) can perform LDPC coding to obtain an LDPC code, using (a parity check matrix H obtained from) a parity check matrix initial value table of the LDPC code with the code length N of 69120 bits, for example, which is longer than 64k bits, and the coding rate r of any of 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, or 14/16, for example.

Furthermore, the LDPC encoder 115 can perform LDPC coding to obtain a new LDPC code, using (a parity check matrix H obtained from) a parity check matrix initial value table of the new LDPC code with the code length N of 17280 bits (17k bits), for example, which is shorter than 64k bits, and the coding rate r of any of 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, or 14/16, for example.

In the case of performing the LDPC coding to the new LDPC code with the code length N of 17280 bits, a parity check matrix initial value table of the new LDPC code is stored in the storage unit 602 of the LDPC encoder 115 (FIG. 8).

FIG. 30 is a diagram illustrating an example of a parity check matrix initial value table (of the type A method) representing the parity check matrix H of the type A code (hereinafter also referred to as the type A code with r=2/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 2/16.

FIG. 31 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type A code (hereinafter also referred to as the type A code with r=3/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 3/16.

FIG. 32 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type A code (hereinafter also referred to as the type A code with r=4/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 4/16.

FIG. 33 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type A code (hereinafter also referred to as the type A code with r=5/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 5/16.

FIG. 34 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type A code (hereinafter also referred to as the type A code with r=6/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 6/16.

FIG. 35 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type A code (hereinafter also referred to as the type A code with r=7/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 7/16.

FIG. 36 is a diagram illustrating an example of a parity check matrix initial value table (of the type B method) representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=7/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 7/16.

FIG. 37 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=8/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 8/16.

FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=9/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 9/16.

FIG. 39 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=10/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 10/16.

FIG. 40 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=11/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 11/16.

FIG. 41 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=12/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 12/16.

FIG. 42 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=13/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 13/16.

FIG. 43 is a diagram illustrating an example of a parity check matrix initial value table representing the parity check matrix H of the type B code (hereinafter also referred to as the type B code with r=14/16) as a new LDPC code with the code length N of 17280 bits and the coding rate r of 14/16.

The new LDPC code is an LDPC code with high performance.

Here, the LDPC code with high performance is an LDPC code obtained from an appropriate parity check matrix H.

The appropriate parity check matrix H is, for example, a parity check matrix that satisfies a predetermined condition that makes a bit error rate (BER) (and a frame error rate (FER)) smaller when the LDPC code obtained from the parity check matrix H is transmitted at low E_(s)/N₀ or E_(b)/N_(o) (signal power to noise power ratio per bit).

The appropriate parity check matrix H can be obtained by, for example, performing a simulation to measure BERs of when LDPC codes obtained from various parity check matrices satisfying the predetermined condition are transmitted at low E_(s)/N_(o).

Examples of the predetermined condition to be satisfied by the appropriate parity check matrix H include a good analysis result obtained by an analysis method of performance of code called density evolution, absence of a loop of the elements of 1, called cycle 4, and the like.

Here, it is known that the decoding performance of the LDPC code is degraded if the elements of 1 are densely packed in the information matrix H_(A) as in the cycle 4, and therefore, absence of the cycle 4 is desirable in the parity check matrix H.

In the parity check matrix H, a minimum value of the length of a loop (loop length) configured by the elements of 1 is called girth. The absence of the cycle 4 means that the girth is greater than 4.

Note that the predetermined condition to be satisfied by the appropriate parity check matrix H can be appropriately determined from the viewpoints of improvement of the decoding performance of the LDPC code, facilitation (simplification) of the decoding processing for the LDPC code, and the like.

FIGS. 44 and 45 are diagrams for describing density evolution by which an analysis result as the predetermined condition to be satisfied by the appropriate parity check matrix H can be obtained.

The density evolution is a code analysis method of calculating an expected value of an error probability for the entire LDPC code (ensemble) with the code length N of ∞ characterized by a degree sequence to be described below.

For example, when increasing a variance of noise from 0 on an AWGN channel, the expected value of the error probability of an ensemble is initially 0, but the expected value becomes not 0 when the variance of noise becomes a certain threshold or greater.

According to the density evolution, good or bad of the performance of the ensemble (appropriateness of the parity check matrix) can be determined by comparing the threshold of the variance of noise (hereinafter also referred to as performance threshold) at which the expected value of the error probability becomes not 0.

Note that, for a specific LDPC code, an ensemble to which the LDPC code belongs is determined, and the density evolution is performed for the ensemble, whereby rough performance of the LDPC code can be predicted.

Therefore, if an ensemble with high performance is found, the LDPC code with high performance can be found from LDPC codes belonging to the ensemble.

Here, the above-described degree sequence indicates what ratio the variable nodes and check nodes having weights of respective values exist to the code length N of the LDPC code.

For example, a regular (3, 6) LDPC code with the coding rate of 1/2 belongs to an ensemble characterized by a degree sequence indicating that the weights (column weights) of all the variable nodes are 3 and the weights (row weights) of all the check nodes are 6.

FIG. 44 illustrates a Tanner graph of such an ensemble.

In the Tanner graph in FIG. 44, N variable nodes illustrated by the circles (o) in FIG. 44 exist, the number N being equal to the code length N, and N/2 check nodes illustrated by the squares (□) in FIG. 44 exist, the number N/2 being equal to a multiplication value obtained by multiplying the code length N by the coding rate of 1/2.

Three edges with an equal column weight are connected to each variable node. Therefore, there are a total of 3N edges connected to the N variable nodes.

Furthermore, six edges with an equal row weight are connected to each check node. Therefore, there are a total of 3N edges connected to the N/2 check nodes.

Moreover, in the Tanner graph in FIG. 44, there is one interleaver.

The interleaver randomly rearranges the 3N edges connected to the N variable nodes and connects each edge after the rearrangement to any of the 3N edges connected to the N/2 check nodes.

The number of patterns for rearranging the 3N edges connected to the N variable nodes in the interleaver is (3N)! (=(3N)×(3N−1)× . . . ×1). Therefore, the ensemble characterized by the degree sequence indicating that the weights of all the variable nodes are 3 and the weights of all the check nodes are 6 is a set of (3N)! LDPC codes.

In the simulation for finding the LDPC code with high performance (appropriate parity check matrix), a multi-edge type ensemble has been used in the density evolution.

In the multi-edge type ensemble, the interleaver which the edges connected to the variable nodes and the edges connected to the check nodes go through is divided into multi edges, whereby characterization of the ensemble is more strictly performed.

FIG. 45 illustrates an example of a Tanner graph of a multi-edge type ensemble.

In the Tanner graph in FIG. 45, there are two interleavers: a first interleaver and a second interleaver.

Furthermore, in the Tanner graph in FIG. 45, v1 variable nodes each having one edge connected to the first interleaver and 0 edges connected to the second interleaver, v₂ variable nodes each having one edge connected to the first interleaver and two edges connected to the second interleaver, and v3 variable nodes each having 0 edges connected to the first interleaver and two edges connected to the second interleaver exist.

Moreover, in the Tanner graph in FIG. 45, c1 check nodes each having two edges connected to the first interleaver and 0 edges connected to the second interleaver, c2 check nodes each having two edges connected to the first interleaver and two edges connected to the second interleaver, and c3 check nodes each having 0 edges connected to the first interleaver and three edges connected to the second interleaver exist.

Here, the density evolution and its implementation are described in, for example, “On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit”, S. Y. Chung, G. D. Forney, T. J. Richardson, R. Urbanke, IEEE Communications Leggers, VOL. 5, NO. 2, February 2001.

In the simulation for finding (the parity check matrix of) the new LDPC code, an ensemble in which the performance threshold that is E_(b)/N₀ (signal power to noise power ratio per bit) at which BER starts to drop (starts to become small) becomes a predetermined value or less has been found by the multi-edge type density evolution, and the LDPC code that makes BER in a case of using one or more quadrature modulations such as QPSK small has been selected from among the LDPC codes belonging to the ensemble, as the LDPC code with high performance.

(The parity check matrix initial value table representing the parity check matrix of) the new LDPC code has been obtained by the above simulation.

Therefore, according to the new LDPC code, favorable communication quality can be secured in data transmission.

FIG. 46 is a diagram for describing the column weights of the parity check matrix H of the type A code as the new LDPC code.

In regard to the parity check matrix H of the type A code, as illustrated in FIG. 46, the column weight of K1 columns from the 1st column of the A matrix and the C matrix is represented as X1, the column weight of the following K2 columns of the A matrix and the C matrix is represented as X2, the column weight of the following K3 columns of the A matrix and the C matrix is represented as X3, and the column weight of the following M1 columns of the C matrix is represented as XM1.

Note that K1+K2+K3 is equal to the information length K, and M1+M2 is equal to the parity length M. Therefore, K1+K2+K3+M1+M2 is equal to the code length N=17280 bits.

Furthermore, in regard to the parity check matrix H of the type A code, the column weight of M1−1 columns from the 1st column of the B matrix is 2, and the column weight of the M1-th column (last column) of the B matrix is 1. Moreover, the column weight of the D matrix is 1 and the column weight of the Z matrix is 0.

FIG. 47 is a diagram illustrating parameters of parity check matrices H of the type A codes (represented by the parity check matrix initial value tables) in FIGS. 30 to 35.

K, X1, K1, X2, K2, X3, K3, XM1, M1, and M2 as parameters of the parity check matrices H of the type A codes of r=2/16, 3/16, 4/16, 5/16, 6/16, and 7/16 are as illustrated in FIG. 47.

The parameters X1, K1, X2, K2, X3, K3, XM1, M1 (or M2) are set to further improve the performance (for example, the error rate or the like) of the LDPC codes.

FIG. 48 is a diagram for describing the column weights of the parity check matrix H of the type B code as the new LDPC code.

In regard to the parity check matrix H of the type B code, as illustrated in FIG. 48, the column weight of KX1 columns from the 1st column is represented as X1, the column weight of the following KX2 columns is represented as X2, the column weight of KX3 columns is represented as X3, the column weight of the following KX4 columns is represented as X4, and the column weight of the following KY1 columns is represented as Y1.

Note that KX1+KX2+KX3+KX4+KY1 is equal to the information length K, and KX1+KX2+KX3+KX4+KY1+M is equal to the code length N=17280 bits.

Furthermore, in regard to the parity check matrix H of the type B code, the column weight of M−1 columns excluding the last one column, of the last M columns, is 2, and the column weight of the last one column is 1.

FIG. 49 is a diagram illustrating parameters of parity check matrices H of the type B codes (represented by the parity check matrix initial value tables) in FIGS. 36 to 43.

K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1, and M as parameters of the parity check matrices H of the type B codes of r=7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 are as illustrated in FIG. 49.

The parameters X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, and KY1 are set so as to further improve the performance of the LDPC codes.

According to the new LDPC code, favorable BER/FER is realized, and a capacity (communication path capacity) close to the Shannon limit is realized.

<Constellation>

FIGS. 50 to 74 are diagrams illustrating examples of constellations adaptable in the transmission system in FIG. 7.

In the transmission system in FIG. 7, for example, a constellation to be used in MODCOD that is a combination of a modulation method (MODulation) and the LDPC code (CODe) can be set for the MODCOD.

One or more constellations can be set for one MODCOD.

As the constellation, there are a uniform constellation (UC) in which arrangement of signal points is uniform and a non uniform constellation (NUC) in which arrangement of signal points are not uniform.

Furthermore, as the NUC, there are a constellation called 1-dimensional (M²-QAM) non-uniform constellation (1D-NUC), a constellation called 2-dimensional (QQAM) non-uniform constellation (2D-NUC), and the like, for example.

In general, the BER is further improved in the 1D-NUC than the UC, and moreover, the BER is further improved in the 2D-NUC than the 1D-NUC.

The constellation with the modulation method of QPSK is the UC. For example, the UC or the 2D-NUC can be adopted as a constellation for the modulation method of 16QAM, 64QAM, 256QAM, or the like. For example, the UC or the 1D-NUC can be adopted as a constellation for the modulation method of 1024QAM, 4096QAM, or the like.

In the transmission system in FIG. 7, for example, constellations defined in ATSC 3.0, DVB-C.2, or the like, and various other constellations that improve the error rate can be used.

In other words, in the case where the modulation method is QPSK, for example, the same UC can be used for the coding rates r of the LDPC codes.

Furthermore, in the case where the modulation method is 16QAM, 64QAM, or 256QAM, for example, the same UC can be used for the coding rates r of the LDPC codes. Moreover, in the case where the modulation method is 16QAM, 64QAM, or 256QAM, for example, different 2D-NUCs can be used for the coding rates r of the LDPC codes, respectively.

Furthermore, in the case where the modulation method is 1024QAM, or 4096QAM, for example, the same UC can be used for each coding rate r of the LDPC code. Moreover, in the case where the modulation method is 1024QAM, or 4096QAM, for example, different 1D-NUCs can be used for the coding rates r of the LDPC codes, respectively.

Here, the UC of QPSK is also described as QPSK-UC, and the UC of 2^(m)QAM is also described as 2^(m)QAM-UC. Furthermore, the 1D-NUC and 2D-NUC of 2^(m)QAM are also described as 2^(m)QAM-1D-NUC and 2^(m)QAM-2D-NUC, respectively.

Hereinafter, some of constellations defined in ATSC 3.0 will be described.

FIG. 50 is a diagram illustrating coordinates of QPSK-UC signal points used for all the coding rates of the LDPC codes defined in ATSC 3.0 in the case where the modulation method is QPSK.

In FIG. 50, “Input Data cell y” indicates a 2-bit symbol to be mapped to QPSK-UC, and “Constellation point z_(s)” indicates a coordinate of a signal point z_(s). Note that an index s of the signal point z_(s) (an index q of a signal point z_(q) as described below is similar) indicates discrete time of symbols (time interval between one symbol and a next symbol).

In FIG. 50, the coordinate of the signal point z_(s) is expressed in the form of a complex number, and j represents an imaginary unit (√/(−1)).

FIG. 51 is a diagram illustrating coordinates of signal points of 16QAM-2D-NUC used for the coding rates r (CR)=2/15, 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15 of the LDPC codes defined in ATSC 3.0 in the case where the modulation method is 16QAM.

In FIG. 51, the coordinate of the signal point z_(s) is expressed in the form of a complex number, and j represents an imaginary unit, similarly to FIG. 50.

In FIG. 51, w#k represents a coordinate of a signal point in the first quadrant of the constellation.

In the 2D-NUC, a signal point in the second quadrant of the constellation is arranged at a position obtained by symmetrically moving a signal point in the first quadrant with respect to a Q axis, and a signal point in the third quadrant of the constellation is arranged at a position obtained by symmetrically moving a signal point in the first quadrant with respect to the origin. Then, a signal point in the fourth quadrant of the constellation is arranged at a position obtained by symmetrically moving a signal point in the first quadrant with respect to an I axis.

Here, in the case where the modulation method is 2^(m)QAM, m bits are regarded as one symbol, and the one symbol is mapped to a signal point corresponding to the symbol.

The m-bit symbol can be expressed by, for example, an integer value of 0 to 2^(m)−1. Now, symbols y(0), y(1), . . . , y(2^(m)−1) expressed by integer values of 0 to 2^(m)−1 can be classified into four groups of symbols y(0) to y(b−1), y(b) to y(2b−1), y(2b) to y(3b−1), and y(3b) to y(4b−1), where b=2^(m)/4.

In FIG. 51, the suffix k of w#k takes an integer value in a range of 0 to b−1, and w#k represents a coordinate of a signal point corresponding to a symbol y(k) in a range of symbols y(0) to y(b−1).

Then, a coordinate of a signal point corresponding to a symbol y(k+b) in a range of symbols y(b) to y(2b−1) is represented as −conj(w#k), and a coordinate of a signal point corresponding to a symbol y(k+2b) in a range of symbols y(2b) to y(3b−1) is represented as conj(w#k). Furthermore, a coordinate of a signal point corresponding to a symbol y(k+3b) in a range of symbols y(3b) to y(4b−1) is represented by −w#k.

Here, conj(w#k) represents a complex conjugate of w#k.

For example, in a case where the modulation method is 16QAM, symbols y(0), y(1), . . . , and y(15) of m=4 bits are classified into four groups of symbols y(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15), where b=2⁴/4=4.

Then, for example, the symbol y(12), of the symbols y(0) to y(15), is a symbol y(k+3b)=y(0+3×4) in the range of symbols y(3b) to y(4b−1)) and k=0, and therefore the coordinate of the signal point corresponding to the symbol y(12) is −w#k=−w0.

Now, w0 in a case where the modulation method is 16QAM and the coding rate r is 9/15 is 0.2386+j0.5296 according to FIG. 51, where the coding rate r (CR) of the LDPC code is, for example, 9/15. Therefore, the coordinate −w0 of the signal point corresponding to the symbol y(12) is −(0.2386+j0.5296).

FIG. 52 is a diagram illustrating examples of coordinates of signal points of 1024QAM-1D-NUC used for the coding rates r (CR)=2/15, 3/15, 4/15, 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15 of the LDPC codes defined in ATSC 3.0 in the case where the modulation method is 1024QAM.

In FIG. 52, u#k represents a real part Re(z_(s)) and an imaginary part Im(z_(s)) of the complex number as the coordinate of the signal point z_(s) of 1D-NUC, and is a component of a vector u=(u0, u1, . . . , u#V−1) called position vector. The number V of the components u#k of the position vector u is given by an expression V=(2^(m))/2.

FIG. 53 is a diagram illustrating a relationship between the symbol y of 1024QAM and (the component u#k of) the position vector u.

Now, it is assumed that the 10-bit symbol y of 1024QAM is expressed as, from the head bit (most significant bit), y_(0,s), y_(1,s), y_(2,s), y_(3,s), y_(4,s), y_(5,s), y_(6,s), y_(7,s), y_(8,s), and y_(9,s).

A in FIG. 53 illustrates a correspondence between the even-numbered 5 bits y_(1,s), y_(3,s), y_(5,s), y_(9,s) of the symbol y, and u#k representing the real part Re(z_(s)) of (the coordinate) of the signal point z_(s) corresponding to the symbol y.

B in FIG. 53 illustrates a correspondence between the odd-numbered 5 bits y_(0,s), y_(2,s), y_(4,s), y_(6,s), y_(8,s) of the symbol y, and u#k representing the imaginary part Im(z_(s)) of the signal point z_(s) corresponding to the symbol y.

In a case where the 10-bit symbol y=(y_(0,s), y_(1,s), y_(2,s), y_(3,s), y_(4,s), y_(5,s), y_(6,s), y_(7,s), y_(8,s), y_(9,s)) of 1024QAM is (0,0,1,0,0,1,1,1,0,0), for example, the odd-numbered 5 bits (y_(0,s), y_(2,s), y_(4,s), y_(6,s), y_(8,s)) are (0, 1, 0, 1, 0) and the even-numbered 5 bits (y_(1,s), y_(3,s), y_(9,s)) are (0, 0, 1, 1, 0).

In A in FIG. 53, the even-numbered 5 bits (0, 0, 1, 1, 0) are associated with u11, and therefore the real part Re(z_(s)) of the signal point z_(s) corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u11.

In B in FIG. 53, the odd-numbered 5 bits (0, 1, 0, 1, 0) are associated with u3, and therefore the imaginary part Im(z_(s)) of the signal point z_(s) corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3.

Meanwhile, when the coding rate r of the LDPC code is 6/15, for example, u3 is 0.1295 and u11 is 0.7196 according to FIG. 52 in regard to the 1D-NUC used in a case where the modulation method is 1024QAM and the coding rate r (CR) of the LDPC code=6/15.

Therefore, the real part Re(z_(s)) of the signal point z_(s) corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u11=0.7196 and the imaginary part Im(z_(s)) is u3=0.1295. As a result, the coordinate of the signal point z_(s) corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is expressed by 0.7196+j0.1295.

Note that the signal points of the 1D-NUC are arranged in a lattice on a straight line parallel to the I axis and a straight line parallel to the Q axis in the constellation. However, the interval between signal points is not constant. Furthermore, average power of the signal points on the constellation can be normalized in transmission of (data mapped to) the signal points. Normalization can be performed by, where the root mean square of absolute values of all (the coordinates of) the signal points on the constellation is P_(ave), multiplying each signal point z_(s) on the constellation by a reciprocal 1/(√P_(ave)) of the square root √P_(ave) of the root mean square value P_(ave).

The transmission system in FIG. 7 can use the constellation defined in ATSC 3.0 as described above.

FIGS. 54 to 65 illustrate coordinates of signal points of UCs defined in DVB-C.2.

In other words, FIG. 54 is a diagram illustrating a real part Re(z_(q)) of a coordinate z_(q) of a signal point of QPSK-UC (UC in QPSK) defined in DVB-C.2. FIG. 55 is a diagram illustrating an imaginary part Im(z_(q)) of a coordinate z_(q) of a signal point of QPSK-UC defined in DVB-C.2.

FIG. 56 is a diagram illustrating a real part Re(z_(q)) of a coordinate z_(q) of a signal point of 16QAM-UC (UC of 16QAM) defined in DVB-C.2. FIG. 57 is a diagram illustrating an imaginary part Im(z_(q)) of a coordinate z_(q) of a signal point of 16QAM-UC defined in DVB-C.2.

FIG. 58 is a diagram illustrating a real part Re(z_(q)) of a coordinate z_(q) of a signal point of 64QAM-UC (UC of 64QAM) defined in DVB-C.2. FIG. 59 is a diagram illustrating an imaginary part Im(z_(q)) of a coordinate z_(q) of a signal point of 64QAM-UC defined in DVB-C.2.

FIG. 60 is a diagram illustrating a real part Re(z_(q)) of a coordinate z_(q) of a signal point of 256QAM-UC (UC of 256QAM) defined in DVB-C.2. FIG. 61 is a diagram illustrating an imaginary part Im(z_(q)) of a coordinate z_(q) of a signal point of 256QAM-UC defined in DVB-C.2.

FIG. 62 is a diagram illustrating a real part Re(z_(q)) of a coordinate z_(q) of a signal point of 1024QAM-UC (UC of 1024QAM) defined in DVB-C.2. FIG. 63 is a diagram illustrating an imaginary part Im(z_(q)) of a coordinate z_(q) of a signal point of 1024QAM-UC defined in DVB-C.2.

FIG. 64 is a diagram illustrating a real part Re(z_(q)) of a coordinate z_(q) of a signal point of 4096QAM-UC (UC of 4096QAM) defined in DVB-C.2. FIG. 65 is a diagram illustrating an imaginary part Im(z_(q)) of a coordinate z_(q) of a signal point of 4096QAM-UC defined in DVB-C.2.

Note that, in FIGS. 54 to 65, y_(i,q) represent the (i+1)th bit from the head of the m-bit symbol (for example, a 2-bit symbol in QPSK) of 2^(m)QAM. Furthermore, average power of the signal points on the constellation can be normalized in transmission of (data mapped to) the signal points of UC. Normalization can be performed by, where the root mean square of absolute values of all (the coordinates of) the signal points on the constellation is P_(ave), multiplying each signal point z_(q) on the constellation by a reciprocal 1/(√P_(ave)) of the square root √P_(ave) of the root mean square value P_(ave).

In the transmission system in FIG. 7, the UC defined in DVB-C.2 as described above can be used.

In other words, the UCs illustrated in FIGS. 54 to 65 can be used for the new LDPC codes (corresponding to the parity check matrix initial value tables) with the code length N of 17280 bits and the coding rates r of 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 in FIGS. 30 to 43.

FIGS. 66 to 74 are diagrams illustrating examples of coordinates of signal points of NUC, which can be used for the new LDPC codes with the code length N of 17280 bits and the coding rates r of 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 in FIGS. 30 to 43.

That is, FIG. 66 is a diagram illustrating examples of a coordinate of a signal point of 16QAM-2D-NUC that can be used for the new LDPC code.

FIG. 67 is a diagram illustrating examples of a coordinate of a signal point of 64QAM-2D-NUC that can be used for the new LDPC code.

FIGS. 68 and 69 are diagrams illustrating examples of a coordinate of a signal point of 256QAM-2D-NUC that can be used for the new LDPC code.

Note that FIG. 69 is a diagram following FIG. 68.

In FIGS. 66 to 69, the coordinate of the signal point z_(s) is expressed in the form of a complex number, and j represents an imaginary unit, similarly to FIG. 51.

In FIGS. 66 to 69, w#k represents a coordinate of a signal point in the first quadrant of the constellation, similarly to FIG. 51.

Here, as described in FIG. 51, when the m-bit symbol can be expressed by, for example, an integer value of 0 to 2^(m)−1 and b=2^(m)/4, the symbols y(0), y(1), . . . , y(2^(m)−1) expressed by integer values of 0 to 2^(m)−1 can be classified into four groups of symbols y(0) to y(b−1), y(b) to y(2b−1), y(2b) to y(3b−1), and y(3b) to y(4b−1).

In FIGS. 66 to 69, the suffix k of w#k takes an integer value in the range of 0 to b−1, and w#k represents a coordinate of a signal point corresponding to the symbol y(k) in the range of symbols y(0) to y(b−1), similarly to FIG. 51.

Moreover, in FIGS. 66 to 69, a coordinate of a signal point corresponding to the symbol y(k+3b) in the range of symbols y(3b) to y(4b−1) is represented by −w#k, similarly to FIG. 51.

Note that, in FIG. 51, a coordinate of a signal point corresponding to the symbol y(k+b) in the range of symbols y(b) to y(2b−1) is represented as −conj(w#k), and a coordinate of a signal point corresponding to the symbol y(k+2b) in the range of symbols y(2b) to y(3b−1) is represented as conj(w#k). However, the sign of conj is inverted in FIGS. 66 to 69.

In other words, in FIGS. 66 to 69, a coordinate of a signal point corresponding to the symbol y(k+b) in the range of symbols y(b) to y(2b−1) is represented as conj(w#k), and a coordinate of a signal point corresponding to the symbol y(k+2b) in the range of symbols y(2b) to y(3b−1) is represented as −conj(w#k).

FIG. 70 is a diagram illustrating examples of a coordinate of a signal point of 1024QAM-1D-NUC that can be used for the new LDPC code.

In other words, FIG. 70 is a diagram illustrating a relationship between the real part Re(z_(s)) and the imaginary part Im(z_(s)) of the complex number as the coordinate of the signal point z_(s) of 1024QAM-1D-NUC and the (component u#k of) the position vector u.

FIG. 71 is a diagram illustrating the relationship between the symbol y of 1024QAM and (the component u#k of) the position vector u in FIG. 70.

In other words, now, it is assumed that the 10-bit symbol y of 1024QAM is expressed as, from the head bit (most significant bit), y_(0,s), y_(1,s), y_(2,s), y_(3,s), y_(4,s), y_(5,s), y_(6,s), y_(7,s), y_(8,s), and y_(9,s).

A in FIG. 71 illustrates a correspondence between the odd-numbered 5 bits y_(0,s), y_(2,s), y_(4,s), y_(6,s), y_(8,s) from (the head of) the 10-bit symbol y, and the position vector u#k representing the real part Re(z_(s)) of (the coordinate of) the signal point z_(s) corresponding to the symbol y.

B in FIG. 71 illustrates a correspondence between the even-numbered 5 bits y_(1,s), y_(3,s), y_(5,s), y_(7,s), y_(9,s) of the 10-bit symbol y, and the position vector u#k representing the imaginary part Im(z_(s)) of the signal point z_(s) corresponding to the symbol y.

Since the way of obtaining the coordinate of the signal point z_(s) of when the 10-bit symbol y of 1024QAM is mapped to the signal point z_(s) of 1024QAM-1D-NUC defined in FIGS. 70 and 71 is similar to the case described in FIGS. 52 and 53, description is omitted.

FIG. 72 is a diagram illustrating examples of a coordinate of a signal point of 4096QAM-1D-NUC that can be used for the new LDPC code.

In other words, FIG. 72 is a diagram illustrating a relationship between the real part Re(z_(s)) and the imaginary part Im(z_(s)) of the complex number as the coordinate of the signal point z_(s) of 4096QAM-1D-NUC and the position vector u (u#k).

FIGS. 73 and 74 are diagrams illustrating the relationship between the symbol y of 4096QAM and (the component u#k of) the position vector u in FIG. 72.

In other words, now, it is assumed that the 12-bit symbol y of 4096QAM is expressed as, from the head bit (most significant bit), y_(0,s), y_(1,s), y_(2,s), y_(3,s), y_(4,s), y_(5,s), y_(6,s), y_(7,s), y_(8,s), y_(9,s), y_(10,s), and y_(11,s).

FIG. 73 illustrates a correspondence between the odd-numbered 6 bits y_(0,s), y_(2,s), y_(4,s), y_(6,s), y_(8,s), y_(10,s) of the 12-bit symbol y, and the position vector u#k representing the real part Re(z_(s)) of the signal point z_(s) corresponding to the symbol y.

FIG. 74 illustrates a correspondence between the even-numbered 6 bits y_(1,s), y_(3,s), y_(5,s), y_(7,s), y_(9,s), y_(11,s) of the 12-bit symbol y, and the position vector u#k representing the imaginary part Im(z_(s)) of the signal point z_(s) corresponding to the symbol y.

Since the way of obtaining the coordinate of the signal point z_(s) of when the 12-bit symbol y of 4096QAM is mapped to the signal point z_(s) of 4096QAM-1D-NUC defined in FIGS. 72 to 74 is similar to the case described in FIGS. 52 and 53, description is omitted.

Note that average power of the signal points on the constellation can be normalized in transmission of (data mapped to) the signal points of the NUCs in FIGS. 66 to 74. Normalization can be performed by, where the root mean square of absolute values of all (the coordinates of) the signal points on the constellation is P_(ave), multiplying each signal point z_(s) on the constellation by a reciprocal 1/(√P_(ave)) of the square root √P_(ave) of the root mean square value P_(ave). Furthermore, in FIG. 53 described above, the odd-numbered bits of the symbol y are associated with the position vector u#k representing the imaginary part Im(z_(s)) of the signal point z_(s) and the even-numbered bits of the symbol y are associated with the position vector u#k representing the real part Re(z_(s)) of the signal point z_(s). In FIG. 71, and FIGS. 73 and 74, conversely, the odd-numbered bits of the symbol y are associated with the position vector u#k representing the real part Re(z_(s)) of the signal point z_(s) and the even-numbered bits of the symbol y are associated with the position vector u#k representing the imaginary part Im(z_(s)) of the signal point z_(s).

<Block Interleaver 25>

FIG. 75 is a diagram for describing block interleaving performed by the block interleaver 25 in FIG. 9.

The block interleaving is performed by dividing the LDPC code of one codeword into a part called part 1 and a part called part 2 from the head of the LDPC code.

Npart 1+Npart 2 is equal to the code length N, where the length (bit length) of part 1 is Npart 1 and the length of part 2 is Npart 2.

Conceptually, in the block interleaving, columns as storage regions each storing Npart1/m bits in a column (vertical) direction as one direction are arranged in a row direction orthogonal to the column direction by the number m equal to the bit length m of the symbol, and each column is divided from the top into a small unit of 360 bits that is the parallel factor P. This small unit of column is also called column unit.

In the block interleaving, as illustrated in FIG. 75, writing of part 1 of the LDPC code of one codeword downward (in the column direction) from the top of the first column unit of the column is performed in the columns from left to right direction.

Then, when the writing to the first column unit of the rightmost column is completed, the writing returns to the leftmost column, and writing downward from the top of the second column unit of the column is performed in the columns from the left to right direction, as illustrated in FIG. 75. Hereinafter, writing of part 1 of the LDPC code of one codeword is similarly performed.

When the writing of part 1 of the LDPC code of one codeword is completed, part 1 of the LDPC code is read in units of m bits in the row direction from the first column of all the m columns, as illustrated in FIG. 75.

The unit of m bits of part 1 is supplied from the block interleaver 25 to the mapper 117 (FIG. 8) as the m-bit symbol.

The reading of part 1 in units of m bits is sequentially performed toward lower rows of the m columns. When the reading of part 1 is completed, part 2 is divided into units of m bits from the top and is supplied from the block interleaver 25 to the mapper 117 as the m-bit symbol.

Therefore, part 1 is symbolized while being interleaved, and part 2 is sequentially dividing into m bits and symbolized without being interleaved.

Npart1/m as the length of the column is a multiple of 360 as the parallel factor P, and the LDPC code of one codeword is divided into part 1 and part 2 so that Npart1/m becomes a multiple of 360.

FIG. 76 is a diagram illustrating examples of part 1 and part 2 of the LDPC code with the code length N of 69120 bits in the case where the modulation method is QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

In FIG. 76, part 1 is 68400 bits and part 2 is 720 bits in a case where the modulation method is 1024QAM, and part 1 is 69120 bits and part 2 is 0 bits in cases where the modulation methods are QPSK, 16QAM, 64QAM, 256QAM, and 4096QAM.

<Group-Wise Interleaving>

FIG. 77 is a diagram for describing group-wise interleaving performed by the group-wise interleaver 24 in FIG. 9.

In the group-wise interleaving, as illustrated in FIG. 77, the LDPC code of one codeword is interleaved in units of bit groups according to a predetermined pattern (hereinafter also referred to as GW pattern) where one section of 360 bits is set as a bit group, the one section of 360 bits being obtained by dividing the LDPC code of one codeword into units of 360 bits, the unit being equal to the parallel factor P, from the head of the LDPC code.

Here, the (i+1)th bit group from the head of when the LDPC code of one codeword is divided into bit groups is hereinafter also described as bit group i.

In a case where the parallel factor P is 360, for example, an LDPC code with the code length N of 1800 bits is divided into 5 (=1800/360) bit groups of bit groups 0, 1, 2, 3, and 4. Moreover, for example, an LDPC code with the code length N of 69120 bits is divided into 192 (=69120/360) bit groups of the bit groups 0, 1, . . . , 191. Moreover, for example, an LDPC code with the code length N of 17280 bits is divided into 48 (=17280/360) bit groups of the bit groups 0, 1, . . . , 47.

Hereinafter, the GW pattern is represented by a sequence of numbers representing a bit group. For example, regarding the LDPC code of five bit groups 0, 1, 2, 3, and 4 with the code length N of 1800 bits, GW patterns 4, 2, 0, 3, and 1 represent interleaving (rearranging) a sequence of the bit groups 0, 1, 2, 3, and 4 with a sequence of the bit groups 4, 2, 0, 3, and 1, for example.

For example, now, it is assumed that the (i+1)th code bit from the head of the LDPC code with the code length N of 1800 bits is represented by x_(i).

In this case, according to the group-wise interleaving of the GW patterns 4, 2, 0, 3, and 1, the 1800-bit LDPC code {x₀, x₁, . . . , x₁₇₉₉} is interleaved with arrangement of {x₁₄₄₀, x₁₄₄₁, . . . , x₁₇₉₉}, {x₇₂₀, x₇₂₁, . . . , x₁₀₇₉}, {x₀, x₁, . . . , x₃₅₉}, {x₁₀₈₀, x₁₀₈₁, . . . , x₁₄₃₉} and {x₃₆₀, x₃₆₁, . . . , x₇₁₉}.

The GW pattern can be set for each code length N of the LDPC code, each coding rate r, each modulation method, each constellation, or each combination of two or more of the code length N, the coding rate r, the modulation method, and the constellation.

Example of GW Pattern for LDPC Code

FIG. 78 is a diagram illustrating an example of the GW pattern for the LDPC code with the code length N of 69120 bits.

According to the GW pattern in FIG. 78, a sequence of bit groups 0 to 191 of the 69120-bit LDPC code is interleaved into a sequence of bit groups 191, 12, 188, 158, 173, 48, 75, 146, 113, 15, 51, 119, 132, 161, 91, 189, 142, 93, 120, 29, 156, 101, 100, 22, 165, 65, 98, 153, 127, 74, 39, 80, 38, 130, 148, 81, 13, 24, 125, 0, 174, 140, 124, 5, 68, 3, 104, 136, 63, 162, 106, 8, 25, 182, 178, 90, 96, 79, 168, 172, 128, 64, 69, 102, 45, 66, 86, 155, 163, 6, 152, 164, 108, 9, 111, 16, 177, 53, 94, 85, 72, 32, 147, 184, 117, 30, 54, 34, 70, 149, 157, 109, 73, 41, 131, 187, 185, 18, 4, 150, 92, 143, 14, 115, 20, 50, 26, 83, 36, 58, 169, 107, 129, 121, 43, 103, 21, 139, 52, 167, 19, 2, 40, 116, 181, 61, 141, 17, 33, 11, 135, 1, 37, 123, 180, 137, 77, 166, 183, 82, 23, 56, 88, 67, 176, 76, 35, 71, 105, 87, 78, 171, 55, 62, 44, 57, 97, 122, 112, 59, 27, 99, 84, 10, 134, 42, 118, 144, 49, 28, 126, 95, 7, 110, 186, 114, 151, 145, 175, 138, 133, 31, 179, 89, 46, 160, 170, 60, 154, 159, 47, 190.

Configuration Example of Reception Device 12

FIG. 79 is a block diagram illustrating a configuration example of the reception device 12 in FIG. 7.

An OFDM processing unit (OFDM operation) 151 receives an OFDM signal from the transmission device 11 (FIG. 7) and performs signal processing for the OFDM signal. Data obtained by performing the signal processing by the OFDM processing unit 151 is supplied to a frame management unit (frame management) 152.

The frame management unit 152 processes (interprets) a frame configured by the data supplied from the OFDM processing unit 151, and supplies a signal of resulting target data and a signal of control data to frequency deinterleavers 161 and 153, respectively.

The frequency deinterleaver 153 performs frequency deinterleaving for the data from the frame management unit 152 in units of symbols, and supplies the data to a demapper 154.

The demapper 154 performs demapping (signal point arrangement decoding) and quadrature demodulation for the data (data on the constellation) from the frequency deinterleaver 153 on the basis of arrangement (constellation) of the signal points determined by the quadrature modulation performed on the transmission device 11 side, and supplies resulting data ((likelihood) of the LDPC code) to an LDPC decoder 155.

The LDPC decoder 155 (decoding unit) performs LDPC decoding for the LDPC code from the demapper 154, and supplies resulting LDPC target data (here, BCH code) to a BCH decoder 156.

The BCH decoder 156 performs BCH decoding for the LDPC target data from the LDPC decoder 155, and outputs resulting control data (signaling).

Meanwhile, the frequency deinterleaver 161 performs frequency deinterleaving in units of symbols for the data from the frame management unit 152, and supplies the data to an SISO/MISO decoder 162.

The SISO/MISO decoder 162 performs space-time decoding of the data from the frequency deinterleaver 161 and supplies the data to a time deinterleaver 163.

The time deinterleaver 163 deinterleaves the data from the SISO/MISO decoder 162 in units of symbols and supplies the data to a demapper 164.

The demapper 164 performs demapping (signal point arrangement decoding) and quadrature demodulation for the data (data on the constellation) from the time deinterleaver 163 on the basis of arrangement (constellation) of the signal points determined by the quadrature modulation performed on the transmission device 11 side, and supplies resulting data to a bit deinterleaver 165.

The bit deinterleaver 165 performs bit deinterleaving for the data from the demapper 164, and supplies (likelihood of) the LDPC code that is data after the bit deinterleaving to the LDPC decoder 166.

The LDPC decoder 166 performs LDPC decoding for the LDPC code from the bit deinterleaver 165, and supplies resulting LDPC target data (here, the BCH code) to a BCH decoder 167.

The BCH decoder 167 performs BCH decoding for the LDPC target data from the LDPC decoder 155, and supplies resulting data to a BB descrambler 168.

The BB descrambler 168 applies BB descrambling to the data from the BCH decoder 167, and supplies resulting data to a null deletion unit 169.

The null deletion unit 169 deletes the null inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168, and supplies the data to the demultiplexer 170.

The demultiplexer 170 demultiplexes each of one or more streams (target data) multiplexed into the data from the null deletion unit 169, applies necessary processing, and outputs a result as an output stream.

Note that the reception device 12 can be configured without including a part of the blocks illustrated in FIG. 79. In other words, in a case where the transmission device 11 (FIG. 8) is configured without including the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, for example, the reception device 12 can be configured without including the time deinterleaver 163, the SISO/MISO decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153 that are blocks respectively corresponding to the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmission device 11.

Configuration Example of Bit Deinterleaver 165

FIG. 80 is a block diagram illustrating a configuration example of the bit deinterleaver 165 in FIG. 79.

The bit deinterleaver 165 is configured by a block deinterleaver 54 and a group-wise deinterleaver 55, and performs (bit) deinterleaving of the symbol bit of the symbol that is the data from the demapper 164 (FIG. 79).

In other words, the block deinterleaver 54 performs, for the symbol bit of the symbol from demapper 164, block deinterleaving corresponding to the block interleaving performed by the block interleaver 25 in FIG. 9 (processing reverse to the block interleaving), in other words, block deinterleaving of returning the positions of (the likelihood of) the code bits of the LDPC code rearranged by the block interleaving to the original positions, and supplies a resulting LDPC code to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs, for example, for the LDPC code from the block deinterleaver 54, group-wise deinterleaving corresponding to the group-wise interleaving performed by the group-wise interleaver 24 in FIG. 9 (processing reverse to the group-wise interleaving), in other words, group-wise deinterleaving of rearranging, in units of bit groups, the code bits of the LDPC code changed in sequence in units of bit groups by the group-wise interleaving described in FIG. 77 to the original sequence.

Here, in a case where the parity interleaving, the group-wise interleaving, and the block interleaving have been applied to the LDPC code to be supplied from the demapper 164 to the bit deinterleaver 165, the bit deinterleaver 165 can perform all of parity deinterleaving corresponding to the parity interleaving (processing reverse to the parity interleaving, in other words, parity deinterleaving of returning the code bits of the LDPC code changed in arrangement by the parity interleaving to the original arrangement), the block deinterleaving corresponding to the block interleaving, and the group-wise deinterleaving corresponding to the group-wise interleaving.

Note that the bit deinterleaver 165 in FIG. 80 is provided with the block deinterleaver 54 for performing the block deinterleaving corresponding to the block interleaving, and the group-wise deinterleaver 55 for performing the group-wise deinterleaving corresponding to the group-wise interleaving, but the bit deinterleaver 165 is not provided with a block for performing the parity deinterleaving corresponding to the parity interleaving and does not perform the parity deinterleaving.

Therefore, the LDPC code for which the block deinterleaving and the group-wise deinterleaving are performed and the parity deinterleaving is not performed is supplied from the (group-wise deinterleaver 55) of the bit deinterleaver 165 to the LDPC decoder 166.

The LDPC decoder 166 performs LDPC decoding for the LDPC code from the bit deinterleaver 165, using a transformed parity check matrix obtained by performing at least column permutation corresponding to the parity interleaving for the parity check matrix H by the type B method used for the LDPC coding by the LDPC encoder 115 in FIG. 8, or a transformed parity check matrix (FIG. 29) obtained by performing row permutation for the parity check matrix (FIG. 27) by the type A method, and outputs resulting data as a decoding result of the LDPC target data.

FIG. 81 is a flowchart for describing processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166 in FIG. 80.

In step S111, the demapper 164 performs demapping and quadrature demodulation for the data (the data on the constellation mapped to the signal points) from the time deinterleaver 163 and supplies the data to the bit deinterleaver 165. The processing proceeds to step S112.

In step S112, the bit deinterleaver 165 performs deinterleaving (bit deinterleaving) for the data from the demapper 164. The process proceeds to step S113.

In other words, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving for the data (symbol) from the demapper 164, and supplies code bits of the resulting LDPC code to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs group-wise deinterleaving for the LDPC code from the block deinterleaver 54, and supplies (the likelihood) of the resulting LDPC code to the LDPC decoder 166.

In step S113, the LDPC decoder 166 performs LDPC decoding for the LDPC code from the group-wise deinterleaver 55 using the parity check matrix H used for the LDPC coding by the LDPC encoder 115 in FIG. 8, in other words, the transformed parity check matrix obtained from the parity check matrix H, for example, and supplies resulting data as a decoding result of the LDPC target data to the BCH decoder 167.

Note that, even in FIG. 80, the block deinterleaver 54 for performing the block deinterleaving and the group-wise deinterleaver 55 for performing the group-wise deinterleaving are separately configured, as in the case in FIG. 9, for convenience of description. However, the block deinterleaver 54 and the group-wise deinterleaver 55 can be integrally configured.

Furthermore, in a case where the group-wise interleaving is not performed in the transmission device 11, the reception device 12 can be configured without including the group-wise deinterleaver 55 for performing the group-wise deinterleaving.

<LDPC Decoding>

The LDPC decoding performed by the LDPC decoder 166 in FIG. 79 will be further described.

The LDPC decoder 166 in FIG. 79 performs the LDPC decoding for the LDPC code from the group-wise deinterleaver 55, for which the block deinterleaving and the group-wise deinterleaving have been performed and the parity deinterleaving has not been performed, using the transformed parity check matrix obtained by performing at least column permutation corresponding to the parity interleaving for the parity check matrix H by the type B method used for the LDPC coding by the LDPC encoder 115 in FIG. 8, or the transformed parity check matrix (FIG. 29) obtained by performing row permutation for the parity check matrix (FIG. 27) by the type A method.

Here, LDPC decoding for enabling suppression of a circuit scale and suppression of an operation frequency within a sufficiently feasible range by being performed using a transformed parity check matrix has been previously proposed (for example, see Japanese Patent No. 4224777).

Therefore, first, the LDPC decoding using a transformed parity check matrix, which has been previously proposed, will be described with reference to FIGS. 82 to 85.

FIG. 82 is a diagram illustrating an example of the parity check matrix H of the LDPC code with the code length N of 90 and the coding rate of 2/3.

Note that, in FIG. 82 (similarly performed in FIGS. 83 and 84 described below), 0 is expressed by a period (.).

In the parity check matrix H in FIG. 82, the parity matrix has a step structure.

FIG. 83 is a diagram illustrating a parity check matrix H′ obtained by applying row permutation of the expression (11) and column permutation of the expression (12) to the parity check matrix H in FIG. 82. Row permutation: (6s+t+1)th row→(5t+s+1)th row  (11) Column permutation: (6x+y+61)th column→(5y+x+61)th column  (12)

Note that, in the expressions (11) and (12), s, t, x, and y are integers in ranges of 0≤s<5, 0≤t<6, 0≤x<5, and 0≤t<6, respectively.

According to the row permutation of the expression (11), permutation is performed in such a manner that the 1, 7, 13, 19, and 25th rows where the remainder becomes 1 when being divided by 6 are respectively permutated to the 1, 2, 3, 4, and 5th rows, and the 2, 8, 14, 20, and 26th rows where the remainder becomes 2 when being divided by 6 are respectively permutated to the 6, 7, 8, 9, and 10th rows.

Furthermore, according to the column permutation of the expression (12), permutation is performed for the 61st and subsequent columns (parity matrix) in such a manner that the 61, 67, 73, 79, and 85th columns where the remainder becomes 1 when being divided by 6 are respectively permutated to the 61, 62, 63, 64, and 65th columns, and the 62, 68, 74, 80, and 86th columns where the remainder becomes 2 when being divided by 6 are respectively permutated to the 66, 67, 68, 69, and 70th columns.

A matrix obtained by performing the row and column permutation for the parity check matrix H in FIG. 82 is the parity check matrix H′ in FIG. 83.

Here, the row permutation of the parity check matrix H does not affect the arrangement of the code bits of the LDPC code.

Furthermore, the column permutation of the expression (12) corresponds to parity interleaving with the information length K of 60, the parallel factor P of 5, and the divisor q (=M/P) of the parity length M (30 here) of 6, of the parity interleaving of interleaving the position of the (K+Py+x+1)th code bit with the (K+qx+y+1)th code bit.

Therefore, the parity check matrix H′ in FIG. 83 is a transformed parity check matrix obtained by performing at least the column permutation of permutating the (K+qx+y+1)th column of the parity check matrix (hereinafter referred to as original parity check matrix as appropriate) H in FIG. 82 with the (K+Py+x+1)th column.

When multiplying the transformed parity check matrix H′ in FIG. 83 by a resultant obtained by performing the same permutation as the expression (12) for the LDPC code of the original parity check matrix H in FIG. 82, a 0 vector is output. In other words, assuming that a row vector obtained by applying the column permutation of the expression (12) to the row vector c as the LDPC code (one codeword) of the original parity check matrix H is represented by c′, H′c′^(T) naturally becomes a 0 vector because Hc^(T) becomes a 0 vector from the nature of the parity check matrix.

From the above, the transformed parity check matrix H′ in FIG. 83 is a parity check matrix of the LDPC code c′ obtained by performing the column permutation of the expression (12) for the LDPC code c of the original parity check matrix H.

Therefore, a similar decoding result to the case of decoding the LDPC code of the original parity check matrix H using the parity check matrix H can be obtained by performing the column permutation of the expression (12) for the LDPC code c of the original parity check matrix H, decoding (LDPC decoding) the LDPC code c′ after the column permutation using the transformed parity check matrix H′ in FIG. 83, and applying reverse permutation to the column permutation of the expression (12) to the decoding result.

FIG. 84 is a diagram illustrating the transformed parity check matrix H′ in FIG. 83, which is separated in units of 5×5 matrix.

In FIG. 84, the transformed parity check matrix H′ is represented by a combination of an identity matrix of 5×5 (=P×P) as the parallel factor P, a matrix where one or more of is in the identity matrix become 0 (hereinafter, the matrix is referred to as quasi identify matrix), a matrix obtained by cyclically shifting the identity matrix or the quasi identify matrix (hereinafter the matrix is referred to as shift matrix as appropriate), and a sum of two or more of the identity matrix, the quasi identify matrix, and the shift matrix (hereinafter, the matrix is referred to as sum matrix as appropriate), and a 5×5 zero matrix.

It can be said that the transformed parity check matrix H′ in FIG. 84 is configured by the 5×5 identity matrix, the quasi identity matrix, the shift matrix, the sum matrix, and the 0 matrix. Therefore, these 5×5 matrices (the identity matrix, the quasi identity matrix, the shift matrix, the sum matrix, and the 0 matrix) constituting the transformed parity check matrix H′ are hereinafter referred to as configuration matrices as appropriate.

For decoding of an LDPC code of a parity check matrix represented by a P×P configuration matrix, an architecture that simultaneously performs P check node operations and variable node operations can be used.

FIG. 85 is a block diagram illustrating a configuration example of a decoding device that performs such decoding.

In other words, FIG. 85 illustrates a configuration example of a decoding device that decodes the LDPC code using the transformed parity check matrix H′ in FIG. 84 obtained by performing at least the column permutation of the expression (12) for the original parity check matrix H in FIG. 82.

The decoding device in FIG. 85 includes an edge data storage memory 300 including six FIFOs 300 ₁ to 300 ₆, a selector 301 for selecting the FIFOs 300 ₁ to 300 ₆, a check node calculation unit 302, two cyclic shift circuits 303 and 308, an edge data storage memory 304 including eighteen FIFOs 304 ₁ to 304 ₁₈, a selector 305 for selecting the FIFOs 304 ₁ to 304 ₁₈, a received data memory 306 for storing received data, a variable node calculation unit 307, a decoded word calculation unit 309, a received data rearranging unit 310, and a decoded data rearranging unit 311.

First, a method of storing data in the edge data storage memories 300 and 304 will be described.

The edge data storage memory 300 is configured by the six FIFOs 300 ₁ to 300 ₆, the six corresponding to a number obtained by dividing the number of rows of 30 of the transformed parity check matrix H′ in FIG. 84 by the number of rows (parallel factor P) of 5 of the configuration matrix. The FIFO 300 _(y) (y=1, 2, . . . , 6) includes storage regions of a plurality of stages, and messages corresponding to five edges, the five corresponding to the number of rows and the number of columns (parallel factor P) of the configuration matrix, can be read and written at the same time with respect to the storage regions of the respective stages.

Furthermore, the number of stages of the storage regions of the FIFO 300 _(y) is nine that is the maximum value of the number of 1s (Hamming weights) in the row direction of the transformed parity check matrix in FIG. 84.

In the FIFO 300 ₁, data (message v_(i) from the variable node) corresponding to the positions of 1 of the 1st to 5th rows of the transformed parity check matrix H′ in FIG. 84 is stored close to each other (ignoring 0) for each row in the cross direction. In other words, data corresponding to the positions of 1 of the 5×5 identity matrix of from (1, 1) to (5, 5) of the transformed parity check matrix H′ is stored in the storage region of the first stage of the FIFO 300 ₁, where the j-th row i-th column is represented by (j, i). Data corresponding to the positions of 1 of the shift matrix of from (1, 21) to (5, 25) of the transformed parity check matrix H′ (the shift matrix obtained by cyclically shifting the 5×5 identity matrix by only 3 in the right direction) is stored in the storage region of the second stage. Data is stored in association with the transformed parity check matrix H′, similarly in the storage regions of the third to eighth stages. Then, data corresponding to the positions of 1 of the shift matrix of from (1, 86) to (5, 90) of the transformed parity check matrix H′ (the shift matrix obtained by permutating 1 in the 1st row of the 5×5 identity matrix to 0 and cyclically shifting the identity matrix by only 1 in the left direction) is stored in the storage region of the ninth stage.

Data corresponding to the positions of 1 of from the 6th to 10th rows of the transformed parity check matrix H′ in FIG. 84 is stored in the FIFO 300 ₂. In other words, data corresponding to the positions of 1 of a first shift matrix constituting the sum matrix of from (6, 1) to (10, 5) of the transformed parity check matrix H′ (the sum matrix that is a sum of the first shift matrix obtained by cyclically shifting the 5×5 identity matrix by 1 to the right and a second shift matrix obtained by cyclically shifting the 5×5 identity matrix by 2 to the right) is stored in the storage region of the first stage of the FIFO 300 ₂. Furthermore, data corresponding to the positions of 1 of the second shift matrix constituting the sum matrix of from (6, 1) to (10, 5) of the transformed parity check matrix H′ is stored in the storage region of the second stage.

In other words, in regard to the configuration matrix with the weight of 2 or more, when the configuration matrix is expressed by a form of a sum of some matrices of a P×P identity matrix with the weight of 1, a quasi identity matrix in which one or more of the elements of 1 of the identity matrix are 0, and a shift matrix obtained by cyclically shifting the identity matrix or the quasi identity matrix, the data corresponding to the position of 1 of the identity matrix with the weight of 1, the quasi identity matrix, or the shift matrix (message corresponding to the edge which belongs to the identity matrix, the quasi identity matrix, or the shift matrix) is stored in the same address (the same FIFO of FIFOs 300 ₁ to 300 ₆).

Hereinafter, data is stored in association with the transformed parity check matrix H′, similarly in the storage regions of the third to ninth stages.

Data are similarly stored in the FIFO 300 ₃ to 300 ₆ in association with the transformed parity check matrix H′.

The edge data storage memory 304 is configured by the eighteen FIFO 304 ₁ to 304 ₁₈, the eighteen corresponding to a number obtained by dividing the number of columns of 90 of the transformed parity check matrix H′ by the number of columns (parallel factor P) of 5 of the configuration matrix. The FIFO 304 _(x) (x=1, 2, . . . , 18) includes storage regions of a plurality of stages, and messages corresponding to five edges, the five corresponding to the number of rows and the number of columns (parallel factor P) of the configuration matrix, can be read and written at the same time with respect to the storage regions of the respective stages.

In the FIFO 304 ₁, data (message u_(j) from the check node) corresponding to the positions of 1 of the 1st to 5th columns of the transformed parity check matrix H′ in FIG. 84 is stored close to each other (ignoring 0) for each column in the vertical direction. In other words, data corresponding to the positions of 1 of the 5×5 identity matrix of from (1, 1) to (5, 5) of the transformed parity check matrix H′ is stored in the storage region of the first stage of the FIFO 304 ₁. Data corresponding to the positions of 1 of a first shift matrix constituting the sum matrix of from (6, 1) to (10, 5) of the transformed parity check matrix H′ (the sum matrix that is a sum of the first shift matrix obtained by cyclically shifting the 5×5 identity matrix by 1 to the right and a second shift matrix obtained by cyclically shifting the 5×5 identity matrix by 2 to the right) is stored in the storage region of the second stage. Furthermore, data corresponding to the positions of 1 of the second shift matrix constituting the sum matrix of from (6, 1) to (10, 5) of the transformed parity check matrix H′ is stored in the storage region of the third stage.

In other words, in regard to the configuration matrix with the weight of 2 or more, when the configuration matrix is expressed by a form of a sum of some matrices of a P×P identity matrix with the weight of 1, a quasi identity matrix in which one or more of the elements of 1 of the identity matrix are 0, and a shift matrix obtained by cyclically shifting the identity matrix or the quasi identity matrix, the data corresponding to the position of 1 of the identity matrix with the weight of 1, the quasi identity matrix, or the shift matrix (message corresponding to the edge which belongs to the identity matrix, the quasi identity matrix, or the shift matrix) is stored in the same address (the same FIFO of FIFOs 304 ₁ to 304 ₁₉).

Hereinafter, data is stored in association with the transformed parity check matrix H′, similarly in the storage regions of the fourth and fifth stages. The number of stages of the storage regions of the FIFO 304 ₁ is five that is the maximum value of the number of 1s (Hamming weights) in the row direction in the 1st to 5th columns of the transformed parity check matrix H′.

Data is similarly stored in the FIFOs 304 ₂ and 304 ₃ in association with the transformed parity check matrix H′, and respective lengths (stages) are five. Data is similarly stored in the FIFOs 304 ₄ to 304 ₁₂ in association with the transformed parity check matrix H′, and respective lengths are three. Data is similarly stored in the FIFOs 304 ₁₃ and 304 ₁₈ in association with the transformed parity check matrix H′, and respective lengths are two.

Next, the operation of the decoding device in FIG. 85 will be described.

The edge data storage memory 300 includes six FIFOs 300 ₁ to 300 ₆, and selects FIFO to store data from among the six FIFOs 300 ₁ to 300 ₆ according to information (matrix data) D312 indicating which row of the transformed parity check matrix H′ in FIG. 84 five messages D311 supplied from the previous cyclic shift circuit 308 belong to, and collectively stores the five messages D311 to the selected FIFO in order.

Furthermore, in reading data, the edge data storage memory 300 sequentially reads the five messages D300 ₁ from the FIFO 300 ₁ and supplies the read messages to the next selector 301. The edge data storage memory 300 sequentially reads the messages from the FIFOs 300 ₂ to 300 ₆ after completion of the reading of the message from the FIFO 300 ₁, and supplies the messages to the selector 301.

The selector 301 selects the five messages from the FIFO currently being read out, of the FIFOs 300 ₁ to 300 ₆, according to a select signal D301, and supplies the messages as message D302 to the check node calculation unit 302.

The check node calculation unit 302 includes five check node calculators 302 ₁ to 302 ₅, and performs the check node operation according to the expression (7), using the messages D302 (D302 ₁ to D302 ₅) (the messages v_(i) of the expression (7)) supplied through the selector 301, and supplies five messages D303 (D303 ₁ to D303 ₅) obtained as a result of the check node operation (messages u_(j) of the expression (7)) to the cyclic shift circuit 303.

The cyclic shift circuit 303 cyclically shifts the five messages D303 ₁ to D303 ₅ obtained by the check node calculation unit 302, on the basis of information (matrix data) D305 indicating how many identity matrices (or quasi identify matrices), which are the basis of the transformed parity check matrix H′, have been cyclically shifted for the corresponding edge, and supplies a result as a message D304 to the edge data storage memory 304.

The edge data storage memory 304 includes eighteen FIFOs 304 ₁ to 304 ₁₈, and selects FIFO to store data from among the FIFOs 304 ₁ to 304 ₁₈ according to information (matrix data) D305 indicating which row of the transformed parity check matrix H′ five messages D304 supplied from the previous cyclic shift circuit 303 belong to, and collectively stores the five messages D304 to the selected FIFO in order. Furthermore, in reading data, the edge data storage memory 304 sequentially reads five messages D306 ₁ from the FIFO 304 ₁ and supplies the read messages to the next selector 305. The edge data storage memory 304 sequentially reads the messages from the FIFOs 304 ₂ to 304 ₁₈ after completion of the reading of the data from the FIFO 304 ₁, and supplies the messages to the selector 305.

The selector 305 selects the five messages from the FIFO currently being read out, of the FIFOs 304 ₁ to 304 ₅₈, according to a select signal D307, and supplies the messages as message D308 to the variable node calculation unit 307 and the decoded word calculation unit 309.

Meanwhile, the received data rearranging unit 310 rearranges an LDPC code D313 corresponding to the parity check matrix H in FIG. 82, which has been received via the communication path 13, by performing the column permutation of the expression (12), and supplies data as received data D314 to the received data memory 306. The received data memory 306 calculates and stored received LLR (log likelihood ratio) from the received data D314 supplied from the received data rearranging unit 310, and groups five received LLRs and collectively supplies the five received LLRs as a received value D309 to the variable node calculation unit 307 and the decoded word calculation unit 309.

The variable node calculation unit 307 includes five variable node calculators 307 ₁ to 307 ₅, and performs the variable node operation according to the expression (1), using the messages D308 (D308 ₁ to D308 ₅) (messages u_(j) of the expression (1)) supplied via the selector 305, and the five received values D309 (received values u_(0i) of the expression (1)) supplied from the received data memory 306, and supplies messages D310 (D310 ₁ to D310 ₅) (messages v_(i) of the expression (1)) obtained as a result of the operation to the cyclic shift circuit 308.

The cyclic shift circuit 308 cyclically shifts the messages D310 ₁ to D310 ₅ calculated by the variable node calculation unit 307 on the basis of information indicating how many identity matrices (or quasi identify matrices), which are the basis of the transformed parity check matrix H′, have been cyclically shifted for the corresponding edge, and supplies a result as a message D311 to the edge data storage memory 300.

By one round of the above operation, one decoding (variable node operation and check node operation) of the LDPC code can be performed. After decoding the LDPC code a predetermined number of times, the decoding device in FIG. 85 obtains and outputs a final decoding result in the decoded word calculation unit 309 and the decoded data rearranging unit 311.

In other words, the decoded word calculation unit 309 includes five decoded word calculators 3091 to 3095, and calculates, as a final stage of the plurality of times of decoding, the decoding result (decoded word) on the basis of the expression (5), using the five messages D308 (D308 ₁ to D308 ₅) (messages u₁ of the expression (5)) output by the selector 305, and the five received values D309 (received values u_(0i) of the expression (5)) supplied from the received data memory 306, and supplies resulting decoded data D315 to the decoded data rearranging unit 311.

The decoded data rearranging unit 311 rearranges the decoded data D315 supplied from the decoded word calculation unit 309 by performing reverse permutation to the column permutation of the expression (12), and outputs a final decoding result D316.

As described above, by applying at least one or both of the row permutation and the column permutation to the parity check matrix (original parity check matrix) to transform the parity check matrix into a parity check matrix (transformed parity check matrix) that can be represented by a combination of a P×P identity matrix, a quasi identity matrix in which one or more of is in the identity matrix are 0, a shift matrix obtained by cyclically shifting the identity matrix or the quasi identity, a sum matrix that is a sum of two or more of the identity matrix, the quasi identify matrix, and the shift matrix, and a P×P zero matrix, that is, by a combination of the configuration matrices, an architecture to perform P check node operations and variable node operations at the same time for decoding of the LDPC code, the P being a number smaller than the number of rows and the number of columns of the parity check matrix, can be adopted. In the case of adopting the architecture to perform P node operations (check node operations and variable node operations) at the same time, the P being the number smaller than the number of rows and the number of columns of the parity check matrix, a large number of repetitive decodings can be performed while suppressing the operation frequency to the feasible range, as compared with a case of performing the number of node operations at the same time, the number being equal to the number of rows and the number of columns of the parity check matrix.

The LDPC decoder 166 constituting the reception device 12 in FIG. 79 performs the LDPC decoding by performing the P check node operations and variable node operations at the same time, for example, similarly to the decoding device in FIG. 85.

In other words, assuming that the parity check matrix of the LDPC code output by the LDPC encoder 115 constituting the transmission device 11 in FIG. 8 is the parity check matrix H with the parity matrix having a step structure, as illustrated in FIG. 82, for example, to simplify the description, the parity interleaver 23 of the transmission device 11 performs the parity interleaving of interleaving the position of the (K+Py+x+1)th code bit with (K+qx+y+1)th code bit with the setting of the information length K of 60, the parallel factor P of 5, the divisor q (=M/P) of the parity length M of 6.

Since this parity interleaving corresponds to the column permutation of the expression (12) as described above, the LDPC decoder 166 does not need to perform the column permutation of the expression (12).

Therefore, in the reception device 12 in FIG. 79, the LDPC code for which the parity deinterleaving has not been performed, that is, the LDPC code in the state where the column permutation of the expression (12) has been performed, is supplied from the group-wise deinterleaver 55 to the LDPC decoder 166, as described above, and the LDPC decoder 166 performs similar processing to that of the decoding device in FIG. 85 except that the LDPC decoder 166 does not perform the column permutation of the expression (12).

In other words, FIG. 86 is a diagram illustrating a configuration example of the LDPC decoder 166 in FIG. 79.

In FIG. 86, the LDPC decoder 166 is similarly configured to the decoding device in FIG. 85 except that the received data rearranging unit 310 in FIG. 85 is not provided, and performs similar processing to that of the decoding device in FIG. 85 except that the column permutation of the expression (12) is not performed. Therefore, description is omitted.

As described above, since the LDPC decoder 166 can be configured without including the received data rearranging unit 310, the scale can be reduced as compared with the decoding device in FIG. 85.

Note that, in FIGS. 82 to 86, to simplify the description, the code length N of 90, the information length K of 60, the parallel factor (the numbers of rows and columns of the configuration matrix) P of 5, and the divisor q (=M/P) of the parity length M of 6 are set for the LDPC code. However, the code length N, the information length K, the parallel factor P, and the divisor q (=M/P) are not limited to the above-described values.

In other words, in the transmission device 11 in FIG. 8, what the LDPC encoder 115 outputs is the LDPC codes with the code lengths N of 64800, 16200, 69120, 17280, and the like, the information length K of N−Pq (=N−M), the parallel factor P of 360, and the divisor q of M/P, for example. However, the LDPC decoder 166 in FIG. 86 can be applied to a case of performing the LDPC decoding by performing the P check node operations and variable node operations at the same time for such LDPC codes.

Furthermore, after the decoding of the LDPC code in the LDPC decoder 166, the parity part of the decoding result is unnecessary, and in a case of outputting only the information bits of the decoding result, the LDPC decoder 166 can be configured without the decoded data rearranging unit 311.

Configuration Example of Block Deinterleaver 54

FIG. 87 is a diagram for describing block deinterleaving performed by the block deinterleaver 54 in FIG. 80.

In the block deinterleaving, reverse processing to the block interleaving by the block interleaver 25 described in FIG. 75 is performed to return (restore) the sequence of the code bits of the LDPC code to the original sequence.

In other words, in the block deinterleaving, for example, as in the block interleaving, the LDPC code is written and read with respect to m columns, the m being equal to the bit length m of the symbol, whereby the arrangement of the code bits of the LDPC code is returned to the original arrangement.

Note that, in the block deinterleaving, writing of the LDPC code is performed in the order of reading the LDPC code in the block interleaving. Moreover, in the block deinterleaving, reading of the LDPC code is performed in the order of writing the LDPC code in the block interleaving.

In other words, in regard to part 1 of the LDPC code, part 1 of the LDPC code in units of m-bit symbol is written in the row direction from the 1st row of all the m columns, as illustrated in FIG. 87. In other words, the code bit of the LDPC code, which is the m-bit symbol, is written in the row direction.

Writing of part 1 in units of m bits is sequentially performed toward lower rows of the m columns, and when the writing of part 1 is completed, as illustrated in FIG. 87, reading of part 1 downward from the top of the first column unit of the column is performed in the columns from the left to right direction.

When the reading to the rightmost column is completed, the reading returns to the leftmost column, and reading of part 1 downward from the top of the second column unit of the column is performed in the columns from the left to right direction, as illustrated in FIG. 87. Hereinafter, reading of part 1 of the LDPC code of one codeword is similarly performed.

When the reading of part 1 of the LDPC code of one codeword is completed, in regard to part 2 in units of m-bit symbols, the units of m-bit symbols are sequentially concatenated after part 1, whereby the LDPC code in units of symbols is returned to the arrangement of code bits of the LDPC code (the LDCP code before block interleaving) of the original one codeword.

Another Configuration Example of Bit Deinterleaver 165

FIG. 88 is a block diagram illustrating another configuration example of the bit deinterleaver 165 in FIG. 79.

Note that, in FIG. 88, parts corresponding to those in FIG. 80 are given the same reference numerals, and hereinafter, description thereof will be omitted as appropriate.

In other words, the bit deinterleaver 165 in FIG. 88 is similarly configured to the case in FIG. 80 except that a parity deinterleaver 1011 is newly provided.

In FIG. 88, the bit deinterleaver 165 includes the block deinterleaver 54, the group-wise deinterleaver 55, and the parity deinterleaver 1011, and performs bit deinterleaving for the code bits of the LDPC code from the demapper 164.

In other words, the block deinterleaver 54 performs, for the LDPC code from demapper 164, block deinterleaving corresponding to the block interleaving performed by the block interleaver 25 of the transmission device 11 (processing reverse to the block interleaving), in other words, block deinterleaving of returning the positions of the code bits rearranged by the block interleaving to the original positions, and supplies a resulting LDPC code to the group-wise deinterleaver 55.

The group-wise deinterleaver 55 performs, for the LDPC code from the block deinterleaver 54, group-wise deinterleaving corresponding to group-wise interleaving as rearrangement processing performed by the group-wise interleaver 24 of the transmission device 11.

The LDPC code obtained as a result of group-wise deinterleaving is supplied from the group-wise deinterleaver 55 to the parity deinterleaver 1011.

The parity deinterleaver 1011 performs, for the bit codes after the group-wise deinterleaving in the group-wise deinterleaver 55, parity deinterleaving corresponding to the parity interleaving performed by the parity interleaver 23 of the transmission device 11 (processing reverse to the parity interleaving), in other words, parity deinterleaving of returning the arrangement of the code bits of the LDPC code changed in arrangement by the parity interleaving to the original arrangement.

The LDPC code obtained as a result of the parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166.

Therefore, in the bit deinterleaver 165 in FIG. 88, the LDPC code for which the block deinterleaving, the group-wise deinterleaving, and the parity deinterleaving have been performed, in other words, the LDPC code obtained by the LDPC coding according to the parity check matrix H, is supplied to the LDPC decoder 166.

The LDPC decoder 166 performs LDPC decoding for the LDPC code from the bit deinterleaver 165 using the parity check matrix H used for the LDPC coding by the LDPC encoder 115 of the transmission device 11.

In other words, in the type B method, the LDPC decoder 166 performs, for the LDPC code from the bit deinterleaver 165, the LDPC decoding using the parity check matrix H itself (of the type B method) used for the LDPC coding by the LDPC encoder 115 of the transmission device 11 or using the transformed parity check matrix obtained by performing at least column permutation corresponding to the parity interleaving for the parity check matrix H. Furthermore, in the type A method, the LDPC decoder 166 performs, for the LDPC code from the bit deinterleaver 165, the LDPC decoding using the parity check matrix (FIG. 28) obtained by applying column permutation to the parity check matrix (FIG. 27) (of the type A method) used for the LDPC coding by the LDPC encoder 115 of the transmission device 11 or using the transformed parity check matrix (FIG. 29) obtained by applying row permutation to the parity check matrix (FIG. 27) used for the LDPC coding.

Here, in FIG. 88, since the LDPC code obtained by LDPC coding according to the parity check matrix H is supplied from (the parity deinterleaver 1011 of) the bit deinterleaver 165 to the LDPC decoder 166, in a case of performing LDPC decoding of the LDPC code using the parity check matrix H itself by the type B method used for the LDPC coding by the LDPC encoder 115 of the transmission device 11 or using the parity check matrix (FIG. 28) obtained by applying column permutation to the parity check matrix (FIG. 27) by the type A method used for the LDPC coding, the LDPC decoder 166 can be configured as a decoding device for performing LDPC decoding by a full serial decoding method in which operations of messages (a check node message and a variable node message) are sequentially performed for one node at a time or a decoding device for performing LDPC decoding by a full parallel decoding method in which operations of messages are performed simultaneously (parallelly) for all nodes, for example.

Furthermore, in the LDPC decoder 166, in a case of performing LDPC decoding of the LDPC code using the transformed parity check matrix obtained by applying at least column permutation corresponding to the parity interleaving to the parity check matrix H by the type B method used for the LDPC coding by the LDPC encoder 115 of the transmission device 11 or using the transformed parity check matrix (FIG. 29) obtained by applying row permutation to the parity check matrix (FIG. 27) by the type A method used for the LDPC coding, the LDPC decoder 166 can be configured as an architecture decoding device for simultaneously performing the check node operation and the variable node operation for P nodes (or divisors of P other than 1), the architecture decoding device being also a decoding device (FIG. 85) including the received data rearranging unit 310 for rearranging the code bits of the LDPC code by applying column permutation similar to the column permutation (parity interleaving) for obtaining the transformed parity check matrix to the LDPC code.

Note that, in FIG. 88, for convenience of description, the block deinterleaver 54 for performing block deinterleaving, the group-wise deinterleaver 55 for performing group-wise deinterleaving, and the parity deinterleaver 1011 for performing parity deinterleaving are separately configured. However, two or more of the block deinterleaver 54, the group-wise deinterleaver 55, and the parity deinterleaver 1011 can be integrally configured similarly to the parity interleaver 23, the group-wise interleaver 24, and the block interleaver 25 of the transmission device 11.

Configuration Example of Reception System

FIG. 89 is a block diagram illustrating a first configuration example of the reception system to which the reception device 12 is applicable.

In FIG. 89, the reception system includes an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103.

The acquisition unit 1101 acquires a signal including the LDPC code obtained by performing at least the LDPC coding for the LDPC target data such as image data and audio data of a program or the like, via a transmission path (communication path, not illustrated) such as, for example, terrestrial digital broadcasting, satellite digital broadcasting, a cable television (CATV) network, the Internet, or another network, and supplies the signal to the transmission path decoding processing unit 1102.

Here, in a case where the signal acquired by the acquisition unit 1101 is broadcasted from, for example, a broadcasting station via terrestrial waves, satellite waves, cable television (CATV) networks, or the like, the acquisition unit 1101 is configured by a tuner, a set top box (STB), or the like. Furthermore, in a case where the signal acquired by the acquisition unit 1101 is transmitted from a web server by multicast like an internet protocol television (IPTV), for example, the acquisition unit 1101 is configured by, for example, a network interface (I/F) such as a network interface card (NIC).

The transmission path decoding processing unit 1102 corresponds to the reception device 12. The transmission path decoding processing unit 1102 applies transmission path decoding processing including at least processing of correcting an error occurring in the transmission path to the signal acquired by the acquisition unit 1101 via the transmission path, and supplies a resulting signal to the information source decoding processing unit 1103.

In other words, the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by performing at least error correction coding for correcting an error occurring in the transmission path, and the transmission path decoding processing unit 1102 applies the transmission path decoding processing such as the error correction processing to such a signal, for example.

Here, examples of the error correction coding include LDPC coding, BCH coding, and the like. Here, at least the LDPC coding is performed as the error correction coding.

Furthermore, the transmission path decoding processing may include demodulation of a modulated signal, and the like.

The information source decoding processing unit 1103 applies information source decoding processing including at least processing of decompressing compressed information into original information to the signal to which the transmission path decoding processing has been applied.

In other words, compression encoding for compressing information is sometimes applied to the signal acquired by the acquisition unit 1101 via the transmission path in order to reduce the amount of data such as image and sound as the information. In that case, the information source decoding processing unit 1103 applies the information source decoding processing such as processing of decompressing the compressed information into the original information (decompression processing) to the signal to which the transmission path decoding processing has been applied.

Note that, in a case where the compression encoding has not been applied to the signal acquired by the acquisition unit 1101 via the transmission path, the information source decoding processing unit 1103 does not perform the processing of decompressing the compressed information into the original information.

Here, an example of the decompression processing includes MPEG decoding and the like. Furthermore, the transmission path decoding processing may include descrambling and the like in addition to the decompression processing.

In the reception system configured as described above, the acquisition unit 1101 acquires the signal obtained by applying the compression encoding such as MPEG coding to data such as image and sound, for example, and further applying the error correction coding such as the LDPC coding to the compressed data, via the transmission path, and supplies the acquired signal to the transmission path decoding processing unit 1102.

The transmission path decoding processing unit 1102 applies, for example, processing similar to the processing performed by the reception device 12 to the signal from the acquisition unit 1101 as the transmission path decoding processing, and supplies the resulting signal to the information source decoding processing unit 1103.

The information source decoding processing unit 1103 applies the information source decoding processing such as MPEG decoding to the signal from the transmission path decoding processing unit 1102, and outputs resulting image or sound.

The reception system in FIG. 89 as described above can be applied to, for example, a television tuner for receiving television broadcasting as digital broadcasting and the like.

Note that the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be each configured as an independent device (hardware (integrated circuit (IC) or the like) or software module).

Furthermore, the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, or a set of the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, as an independent device.

FIG. 90 is a block diagram illustrating a second configuration example of the reception system to which the reception device 12 is applicable.

Note that, in FIG. 90, parts corresponding to those in FIG. 89 are given the same reference numerals, and hereinafter, description thereof will be omitted as appropriate.

The reception system in FIG. 90 is common to the case in FIG. 89 in including the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 and is different from the case in FIG. 89 in newly including an output unit 1111.

The output unit 1111 is, for example, a display device for displaying an image or a speaker for outputting a sound, and outputs an image, a sound, or the like as a signal output from the information source decoding processing unit 1103. In other words, the output unit 1111 displays an image or outputs a sound.

The reception system in FIG. 90 as described above can be applied to, for example, a television (TV) receiver for receiving television broadcasting as the digital broadcasting, a radio receiver for receiving radio broadcasting, or the like.

Note that, in a case where the compression encoding has not been applied to the signal acquired by the acquisition unit 1101, the signal output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111.

FIG. 91 is a block diagram illustrating a third configuration example of the reception system to which the reception device 12 is applicable.

Note that, in FIG. 90, parts corresponding to those in FIG. 89 are given the same reference numerals, and hereinafter, description thereof will be omitted as appropriate.

The reception system in FIG. 91 is common to the case in FIG. 89 in including the acquisition unit 1101 and the transmission path decoding processing unit 1102.

However, the reception system in FIG. 91 is different from the case in FIG. 89 in not including the information source decoding processing unit 1103 and newly including a recording unit 1121.

The recording unit 1121 records (stores) the signal (for example, a TS packet of TS of MPEG) output by the transmission path decoding processing unit 1102 on a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory.

The reception system in FIG. 91 as described above can be applied to a recorder for recording television broadcasting or the like.

Note that, in FIG. 91, the reception system includes the information source decoding processing unit 1103, and the information source decoding processing unit 1103 can record the signal to which the information source decoding processing has been applied, in other words, the image or sound obtained by decoding, in the recording unit 1121.

Embodiment of Computer

Next, the above-described series of processing can be executed by hardware or software. In a case of executing the series of processing by software, a program that configures the software is installed in a general-purpose computer or the like.

Thus, FIG. 92 illustrates a configuration example of an embodiment of a computer to which a program for executing the above-described series of processing is installed.

The program can be recorded in advance in a hard disk 705 or a ROM 703 as a recording medium built in the computer.

Alternatively, the program can be temporarily or permanently stored (recorded) on a removable recording medium 711 such as a flexible disk, a compact disc read only memory (CD-ROM), a magneto optical (MO) disk, a digital versatile disc (DVD), a magnetic disk, or a semiconductor memory. Such a removable recording medium 711 can be provided as so-called package software.

Note that the program can be installed from the above-described removable recording medium 711 to the computer, can be transferred from a download site to the computer via a satellite for digital satellite broadcasting, or can be transferred by wired means to the computer via a network such as a local area network (LAN) or the internet, and the program thus transferred can be received by a communication unit 708 and installed on the built-in hard disk 705 in the computer.

The computer incorporates a central processing unit (CPU) 702. An input/output interface 710 is connected to the CPU 702 via a bus 701. The CPU 702 executes the program stored in the read only memory (ROM) 703 according to a command when the command is input by the user by an operation of an input unit 707 including a keyboard, a mouse, a microphone, and the like via the input/output interface 710. Alternatively, the CPU 702 loads the program stored in the hard disk 705, the program transferred from the satellite or the network, received by the communication unit 708, and installed in the hard disk 705, or the program read from the removable recording medium 711 attached to a drive 709 and installed in the hard disk 705 to a random access memory (RAM) 704 and executes the program. As a result, the CPU 702 performs the processing according to the above-described flowchart or the processing performed by the configuration of the above-described block diagram. Then, the CPU 702 causes an output unit 706 including a liquid crystal display (LCD), a speaker, and the like to output the processing result, the communication unit 708 to transmit the processing result, and the hard disk 705 to record the processing result, via the input/output interface 710, as necessary, for example.

Here, processing steps describing the program for causing the computer to perform various types of processing does not necessarily need to be processed chronologically according to the order described in the flowcharts, and includes processing executed in parallel or individually (for example, processing by parallel processing or object).

Furthermore, the program may be processed by one computer or may be processed in a distributed manner by a plurality of computers. Moreover, the program may be transferred to a remote computer and executed.

Note that embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

For example, (the parity check matrix initial value table of) the above-described new LDPC code and GW pattern can be used for a satellite channel, a ground wave, a cable (wired channel), and another communication path 13 (FIG. 7). Moreover, the new LDPC code and GW pattern can be used for data transmission other than digital broadcasting.

Note that the effects described in the present specification are merely examples and are not limited, and other effects may be exhibited.

REFERENCE SIGNS LIST

-   11 Transmission device -   12 Reception device -   23 Parity interleaver -   24 Group-wise interleaver -   25 Block interleaver -   54 Block deinterleaver -   55 Group-wise deinterleaver -   111 Mode adaptation/multiplexer -   112 Padder -   113 BB scrambler -   114 BCH encoder -   115 LDPC encoder -   116 Bit interleaver -   117 Mapper -   118 Time interleaver -   119 SISO/MISO encoder -   120 Frequency interleaver -   121 BCH encoder -   122 LDPC encoder -   123 Mapper -   124 Frequency interleaver -   131 Frame builder/resource allocation unit -   132 OFDM generation unit -   151 OFDM processing unit -   152 Frame management unit -   153 Frequency deinterleaver -   154 Demapper -   155 LDPC decoder -   156 BCH decoder -   161 Frequency deinterleaver -   162 SISO/MISO decoder -   163 Time deinterleaver -   164 Demapper -   165 Bit deinterleaver -   166 LDPC decoder -   167 BCH decoder -   168 BB descrambler -   169 Null deletion unit -   170 Demultiplexer -   300 Edge data storage memory -   301 Selector -   302 Check node calculation unit -   303 Cyclic shift circuit -   304 Edge data storage memory -   305 Selector -   306 Received data memory -   307 Variable node calculation unit -   308 Cyclic shift circuit -   309 Decoded word calculation unit -   310 Received data rearranging unit -   311 Decoded data rearranging unit -   601 Coding processing unit -   602 Storage unit -   611 Coding rate setting unit -   612 Initial value table reading unit -   613 Parity check matrix generation unit -   614 Information bit reading unit -   615 Coding parity operation unit -   616 Control unit -   701 Bus -   702 CPU -   703 ROM -   704 RAM -   705 Hard disk -   706 Output unit -   707 Input unit -   708 Communication unit -   709 Drive -   710 Input/output interface -   711 Removable recording medium -   1001 Reverse permutation unit -   1002 Memory -   1011 Parity deinterleaver -   1101 Acquisition unit -   1101 Transmission path decoding processing unit -   1103 Information source decoding processing unit -   1111 Output unit -   1121 Recording unit 

The invention claimed is:
 1. A transmission device comprising: encoding circuitry configured to perform LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 9/16, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 291 817 1023 1118 1168 1195 1419 1763 2507 3005 3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301 6600 6644 7052 7093 7105 7487 133 565 957 1018 1150 1196 1210 1224 1361 1484 2330 2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399 5421 5545 6972 7156 129 365 541 1026 1199 1527 2467 3386 3458 4215 4438 4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745 6973 7251 7329 7336 996 1392 2493 2910 3048 3281 4969 5189 5632 6236 6983 165 2521 2650 2824 3493 4637 5670 6470 266 345 390 2365 2843 3274 4321 5165 245 2173 2274 2687 3763 4284 5562 6564 2787 2970 3503 691 3718 5047 593 969 3593 331 3809 6269 1627 2886 5935 1046 2976 4457 4725 6028 6458 6172 6610 7530 1536 7102 7148 233 2463 4955 826 4319 6969 3073 6675 6774 407 4251 7087 1380 3802 4937 1911 4360 6306 4027 6219 7292 398 1190 1936 250 830 7241 5500 5828 7478 1261 4649
 7237.


2. A transmission method comprising: performing, by encoding circuitry, LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 9/16, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 291 817 1023 1118 1168 1195 1419 1763 2507 3005 3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301 6600 6644 7052 7093 7105 7487 133 565 957 1018 1150 1196 1210 1224 1361 1484 2330 2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399 5421 5545 6972 7156 129 365 541 1026 1199 1527 2467 3386 3458 4215 4438 4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745 6973 7251 7329 7336 996 1392 2493 2910 3048 3281 4969 5189 5632 6236 6983 165 2521 2650 2824 3493 4637 5670 6470 266 345 390 2365 2843 3274 4321 5165 245 2173 2274 2687 3763 4284 5562 6564 2787 2970 3503 691 3718 5047 593 969 3593 331 3809 6269 1627 2886 5935 1046 2976 4457 4725 6028 6458 6172 6610 7530 1536 7102 7148 233 2463 4955 826 4319 6969 3073 6675 6774 407 4251 7087 1380 3802 4937 1911 4360 6306 4027 6219 7292 398 1190 1936 250 830 7241 5500 5828 7478 1261 4649
 7237.


3. A reception device comprising: decoding circuitry configured to decode an LDPC code with a code length N of 17280 bits and a coding rate r of 9/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 291 817 1023 1118 1168 1195 1419 1763 2507 3005 3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301 6600 6644 7052 7093 7105 7487 133 565 957 1018 1150 1196 1210 1224 1361 1484 2330 2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399 5421 5545 6972 7156 129 365 541 1026 1199 1527 2467 3386 3458 4215 4438 4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745 6973 7251 7329 7336 996 1392 2493 2910 3048 3281 4969 5189 5632 6236 6983 165 2521 2650 2824 3493 4637 5670 6470 266 345 390 2365 2843 3274 4321 5165 245 2173 2274 2687 3763 4284 5562 6564 2787 2970 3503 691 3718 5047 593 969 3593 331 3809 6269 1627 2886 5935 1046 2976 4457 4725 6028 6458 6172 6610 7530 1536 7102 7148 233 2463 4955 826 4319 6969 3073 6675 6774 407 4251 7087 1380 3802 4937 1911 4360 6306 4027 6219 7292 398 1190 1936 250 830 7241 5500 5828 7478 1261 4649
 7237.


4. A reception method comprising: decoding, by decoding circuitry, an LDPC code with a code length N of 17280 bits and a coding rate r of 9/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 291 817 1023 1118 1168 1195 1419 1763 2507 3005 3886 3952 4046 4924 5372 5586 5742 5925 6080 6157 6301 6600 6644 7052 7093 7105 7487 133 565 957 1018 1150 1196 1210 1224 1361 1484 2330 2448 2525 2583 2639 3198 3407 3504 4272 4383 5133 5399 5421 5545 6972 7156 129 365 541 1026 1199 1527 2467 3386 3458 4215 4438 4778 5176 5484 5521 5540 5788 6103 6287 6360 6605 6745 6973 7251 7329 7336 996 1392 2493 2910 3048 3281 4969 5189 5632 6236 6983 165 2521 2650 2824 3493 4637 5670 6470 266 345 390 2365 2843 3274 4321 5165 245 2173 2274 2687 3763 4284 5562 6564 2787 2970 3503 691 3718 5047 593 969 3593 331 3809 6269 1627 2886 5935 1046 2976 4457 4725 6028 6458 6172 6610 7530 1536 7102 7148 233 2463 4955 826 4319 6969 3073 6675 6774 407 4251 7087 1380 3802 4937 1911 4360 6306 4027 6219 7292 398 1190 1936 250 830 7241 5500 5828 7478 1261 4649
 7237.


5. A transmission device comprising: encoding circuitry configured to perform LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 10/16, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 579 608 613 760 795 839 910 1895 2239 2535 2670 2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166 6352 263 291 694 1172 1232 1925 2657 3037 3057 3400 3550 3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157 6227 527 601 1254 1476 1760 2070 2099 2725 2961 3529 3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087 6446 235 319 480 2036 2188 2358 2423 2510 2911 3225 3472 3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477 1809 2974 3464 5295 5490 5671 2148 3629 4304 4854 4876 6037 2031 2246 3358 4679 6125 6331 874 2483 2964 3872 4509 4904 4001 4303 5079 1652 4524 5263 2551 3381 5524 713 1908 6304 2722 3347 6201 433 923 5564 2181 4242 6202 51 2711 4435 414 708 5539 2222 5036 5974 784 3588 5125 4256 5004 5540 1761 2781 6037 1547 2266 4377 4109 5836 6337 767 2468 4764 2528 5457 5872 884 4651 4807 161 3582 5164 744 2624 4852 239 1740 5807 33 3595
 5121.


6. A transmission method comprising: performing, by encoding circuitry, LDPC coding on a basis of a parity check matrix of an LDPC code with a code length N of 17280 bits and a coding rater of 10/16, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 579 608 613 760 795 839 910 1895 2239 2535 2670 2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166 6352 263 291 694 1172 1232 1925 2657 3037 3057 3400 3550 3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157 6227 527 601 1254 1476 1760 2070 2099 2725 2961 3529 3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087 6446 235 319 480 2036 2188 2358 2423 2510 2911 3225 3472 3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477 1809 2974 3464 5295 5490 5671 2148 3629 4304 4854 4876 6037 2031 2246 3358 4679 6125 6331 874 2483 2964 3872 4509 4904 4001 4303 5079 1652 4524 5263 2551 3381 5524 713 1908 6304 2722 3347 6201 433 923 5564 2181 4242 6202 51 2711 4435 414 708 5539 2222 5036 5974 784 3588 5125 4256 5004 5540 1761 2781 6037 1547 2266 4377 4109 5836 6337 767 2468 4764 2528 5457 5872 884 4651 4807 161 3582 5164 744 2624 4852 239 1740 5807 33 3595
 5121.


7. A reception device comprising: decoding circuitry configured to decode an LDPC code with a code length N of 17280 bits and a coding rate r of 10/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 579 608 613 760 795 839 910 1895 2239 2535 2670 2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166 6352 263 291 694 1172 1232 1925 2657 3037 3057 3400 3550 3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157 6227 527 601 1254 1476 1760 2070 2099 2725 2961 3529 3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087 6446 235 319 480 2036 2188 2358 2423 2510 2911 3225 3472 3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477 1809 2974 3464 5295 5490 5671 2148 3629 4304 4854 4876 6037 2031 2246 3358 4679 6125 6331 874 2483 2964 3872 4509 4904 4001 4303 5079 1652 4524 5263 2551 3381 5524 713 1908 6304 2722 3347 6201 433 923 5564 2181 4242 6202 51 2711 4435 414 708 5539 2222 5036 5974 784 3588 5125 4256 5004 5540 1761 2781 6037 1547 2266 4377 4109 5836 6337 767 2468 4764 2528 5457 5872 884 4651 4807 161 3582 5164 744 2624 4852 239 1740 5807 33 3595
 5121.


8. A reception method comprising: decoding, by decoding circuitry, an LDPC code with a code length N of 17280 bits and a coding rate r of 10/16, the LDPC code being generated on a basis of a parity check matrix of the LDPC code, wherein the LDPC code includes information bits and parity bits, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix portion for every 360 columns, and is 579 608 613 760 795 839 910 1895 2239 2535 2670 2871 3127 3316 3779 3829 3936 4454 4772 4926 6048 6166 6352 263 291 694 1172 1232 1925 2657 3037 3057 3400 3550 3812 4185 4325 5202 5441 5479 5640 5864 5892 6154 6157 6227 527 601 1254 1476 1760 2070 2099 2725 2961 3529 3591 4324 4393 4462 4841 5070 5480 5698 5856 5865 6087 6446 235 319 480 2036 2188 2358 2423 2510 2911 3225 3472 3677 3840 4409 4574 4892 5119 5548 5805 5901 6290 6477 1809 2974 3464 5295 5490 5671 2148 3629 4304 4854 4876 6037 2031 2246 3358 4679 6125 6331 874 2483 2964 3872 4509 4904 4001 4303 5079 1652 4524 5263 2551 3381 5524 713 1908 6304 2722 3347 6201 433 923 5564 2181 4242 6202 51 2711 4435 414 708 5539 2222 5036 5974 784 3588 5125 4256 5004 5540 1761 2781 6037 1547 2266 4377 4109 5836 6337 767 2468 4764 2528 5457 5872 884 4651 4807 161 3582 5164 744 2624 4852 239 1740 5807 33 3595
 5121. 